多重閘極金氧半場效電晶體的變異特性模擬與分析

Abstract

本論文藉由元件模擬器，對多重閘極金氧半電晶體做三維的元件模擬，探討製程參數漂移及隨機摻雜變動對多重閘極金氧半電晶體的起始電壓的影響。 鰭狀電晶體，三閘電晶體及類似平面電晶體分別於三種不同的基底：厚埋層氧化層（100nm，類型一），矽基底（類型二）及薄埋層氧化層（10nm，類型三）將被進行模擬、分析與探討。 通道長度、鰭狀通道寬度(fin-width)、鰭狀通道高度(fin-height)、閘極氧化層厚度、通道摻雜濃度等製程參數的漂移及隨機摻雜變動，對元件起始電壓所造成的影響，將被逐一探討。此外，埋層氧化層的厚度及矽基底，對多重閘極電晶體的起始電壓的影響，也將一併探討。 由模擬的結果，我們可以得知：在相同總通道寬度(Wtotal)的情況下，對低摻雜通道元件，鰭狀電晶體因對製程參數漂移及隨摻雜變動有較高的忍受度，而具有最小的起始電壓變量；然而對高摻摻雜元件，類似平面電晶體則因為具有較小的隨機摻雜變動量，具有較小的起始電壓變量。

This study investigates the threshold voltage (Vth) variation of multi-gate devices using 3-D device simulation. FinFET, Tri-gate and Quasi-planar device structures on thick buried oxide (100nm, scenario 1), bulk (scenario 2) and thin buried oxide (10nm, scenario 3) are examined.

The Vth dispersion caused by variation of the process parameters such as gate length, gate oxide thickness, channel doping, fin width and fin height have been investigated. In addition, the impact of random dopant fluctuation of channel doping on Vth has also been examined. Besides, the impact of buried oxide thickness and bulk substrate on the Vth variation of multi-gate MOSFETs are studied.

Our simulation results indicate that, for lightly doped devices, FinFET structure shows the smallest Vth dispersion because of its better immunity to process-induced variations and random dopant fluctuation. For heavily doped devices, Quasi-planar structure shows smaller Vth dispersion because of its smaller random dopant fluctuation.