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dc.contributor.authorChen, Chia-Peien_US
dc.contributor.authorYang, Ming-Jenen_US
dc.contributor.authorHuang, Hsun-Hsiuen_US
dc.contributor.authorChiang, Tung-Yingen_US
dc.contributor.authorChen, Jheng-Liangen_US
dc.contributor.authorChen, Ming-Chiehen_US
dc.contributor.authorWen, Kuei-Annen_US
dc.date.accessioned2014-12-08T15:08:11Z-
dc.date.available2014-12-08T15:08:11Z-
dc.date.issued2009-12-01en_US
dc.identifier.issn1549-8328en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSI.2009.2016184en_US
dc.identifier.urihttp://hdl.handle.net/11536/6382-
dc.description.abstractA technique of time-to-digital conversion is utilized in a digital demodulator for a low-power 2.4-GHz CMOS GFSK transceiver. The proposed time-to-digital converter (TDC) employs a self-sampling technique and an auto-calibration algorithm to avoid edge synchronization problems and the need of a delay-locked loop (DLL). With the TDC, a limiter and a digital demodulator can be employed simultaneously in the receiver to achieve low power consumption and high performance. Additionally, in the transmitter, the open-loop VCO modulation is adopted to save hardware and power consumption. The transmitter frequency drift in open-loop modulation and frequency offset between the receiver and the transmitter can be easily resolved by the proposed receiver architecture. All required building blocks of the proposed transceiver, except a RF matching network and a crystal, were implemented on a 4-mm(2) chip by a 0.18-mu m CMOS process. The receiver achieves -89-dBm sensitivity at 0.1% BER with 1-Mb/s data rate, and the transmitter delivers up to 0-dBm output power. The receiver and transmitter consume 13.3 mA and 10.7 mA, respectively, from a 1.8-V power supply.en_US
dc.language.isoen_USen_US
dc.subjectComplex bandpass filteren_US
dc.subjectdemodulatoren_US
dc.subjectfrequency synthesizeren_US
dc.subjectlow-noise amplifier (LNA)en_US
dc.subjectopen-loop VCO modulationen_US
dc.subjecttime-to-digital converter (TDC)en_US
dc.titleA Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversionen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSI.2009.2016184en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERSen_US
dc.citation.volume56en_US
dc.citation.issue12en_US
dc.citation.spage2738en_US
dc.citation.epage2748en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000273568400004-
dc.citation.woscount13-
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