考慮再回流製程之派工法則

Abstract

本研究針對晶圓製造之派工問題，運用啟發式的方法建構簡易之派工法則。本研究對於晶圓製造廠在派工上所考慮的派工因子有等候時限問題、重做問題、交期問題、在製品存量問題。每一問題視為派工法則上的單一考慮因子，對於每個因子給予權重值以凸顯出該問題的重要性，而權重的大小以機會成本的概念決定。 本研究以Simple++模擬程式進行模擬驗證。實驗以兩組對造派工模式進行，一為晶圓製造常用者，包含有FIFO及SPT；另一則以交期為主者，包括EDD及Slack兩種，期證明本研究所提出之簡易派工法則能夠在交期的前提下，同時解決多項考慮因子。模擬結果也證明本研究所提之派工法則的確能有效達成上述之目標。

This thesis develops a heuristic dispatching rule for wafer fabrication. Queue-time limit, rework, due date, WIP and so on are some key factors to be considered in the proposed dispatching rule. To demonstrate the effectiveness of the proposed dispatching rule, a simple++ simulation model with real fabrication data is employed. Two sets of conventional dispatching rules : (1)commonly used rules includes FIFO and SPT and (2)due-date-based rules including EDD and Slack. Results show that the proposed dispatching rule does give a better performance.