雙層式軌跡型快取記憶體

Abstract

我們提出一個階層式軌跡型快取記憶體(trace cache)以增加軌跡型快取記憶體的容量。這個機制稱為雙層式軌跡型快取記憶體，它同時採用了階層式記憶體與軌跡型快取記憶體的概念。藉由評估讀寫策略，我們建構出一個雙層式軌跡型快取記憶體的模型。也建立起不同階層的記憶體大小，造成的等效能曲線。除外，我們提出了一種隱藏讀寫時間的設計方式。這個設計方式稱為提早提取的設計，它嘗試在提取的需求出現之前，預測並提前提取所需要的資料。同樣地，我們也為此一額外設計的雙層式軌跡型快取記憶體建立起其模型。在我們的實驗中顯示，當第一與第二層軌跡型快取記憶體的讀寫時間分別是1與2個時脈週期時，我們可以藉由減半第一層軌跡型快取記憶體的容量，而同時加倍第二層軌跡型快取記憶體的容量，來達到相同的系統效能。

We proposed a hierarchical trace cache mechanism to increase the capacity of trace cache. This mechanism, called two level trace cache, employs both the concept of memory hierarchy and trace cache technique. By evaluating read and write policies of trace cache, we construct a model of two level trace cache. The performance isometry of the capacity between different level of trace cache also established. Moreover, we proposed a design to conceal the effect of access latency in two level trace cache. This design, called early fetch design, tries to predict and fetch without blocking earlier than fetch requirement comes out. We also construct a model of two level trace cache with early fetch design. Our experiment had shown that, with 1 and 2 clock cycle access latency of first-level and second-level trace cache respectively, we can reduce the size of first-level trace cache to half, and double the size of second-level trace cache to get same system performance.