基於指令長度預測的高頻寬多指令擷取

Abstract

指令擷取是微處理器管線中的第一級，因此對於微處理器尤其是超純量微處理器的效能有相當大的影響。在超純量微處理器中，指令擷取器每一週期必須提供數個指令給解碼器。然而在x86架構下，由於不定長度指令使得在一個時脈週期內要擷取多個指令相當困難。 在此論文中，我們提出指令識別器的方法，此方法藉由預測指令長度與利用表格儲存指令指標來同時提供數個指令給指令擷取器。突破過去達到高超純量程度(superscalar degree)的困難，加速了指令擷取的效能。 模擬結果建議在效能/花費的考量下，64個表格條目(entry)為適當的選擇。模擬結果也顯示表格的條目越少，預測的方法越重要。另外，模擬和合成(synthesis)的結果顯示我們提出的架構在0.6微米(micron)的製程下，可以達到200MHz。

Because instruction fetch is the first pipeline stage in a microprocessor, it significantly influences the performance of a microprocessor, especially superscalar microprocessor. In a superscalar microprocessor, the instruction fetcher must provide multiple instructions to the decoders each cycle. However, in the x86 architecture, the variable-length instruction makes fetching multiple instructions in a clock cycle difficult. In this thesis, we propose an approach, Instruction Identifier, which can easily provide multiple instruction pointers to the fetcher simultaneously by means of predicting instruction length and storing the instruction pointers to the table. It breaks the difficulty of achieving high superscalar degree (>3) and speeds up the instruction fetching performance. Simulation results suggest that 64-entry table is the proper choice under performance/cost consideration. And simulation results also show that the more the number of entries in the table decreases, the more the prediction scheme becomes important. Besides, simulation and synthesis results show that our design can attain 200 MHz in 0.6-micron process technology.