以N2O氣體之快速加熱氮化於複晶矽氧化層及薄膜電晶體之研究

Abstract

在此論文中主要是研究以N2O氣體之快速加熱氮化應用於複晶矽氧化層及薄膜電晶體。 首先，我們探討了在不同的溫度及厚度下使用N2O氣體以快速加熱氧化的方式成長複晶 矽氧化層之電特性，並與O2氣體成長的複晶矽氧化層作比較。 由實驗結果顯示，於N2O 氧化中摻入適量的氮在複晶矽氧化層中能改善複晶矽與複晶矽氧化層的界面，因此也改 善了複晶矽氧化層的電性。然而於較高的N2O成長溫度 (如105℃) 釋放過多的氮，不會 改善反而會劣化了複晶矽氧化層的品質，並且造成了厚度分佈的不均勻。因此，我們提 出二段式快速加熱的製程，意即首先於O2氣體環境中氧化複晶矽，然後再施以N2O氣體之 快速加熱氮化，因為在第二階段氮化能摻入適量的氮於複晶矽氧化層中而達到所需特性。 然後，我們提出以TEOS化學氣相沉積氧化層沉積在同步磷摻入的複晶矽上，再施以快速 加熱之N2O氮化，能使氧化層有很好的電荷捕獲率，以及大到11庫侖的崩潰電荷量。 由此可發現使用同步磷摻入可取代傳統POCl3的磷摻入而得到較為平坦的複晶矽與複晶矽 氧化層界面，並且再加上快速加熱之N2O氮化，除了使TEOS沉積氧化層緻密外，並且累積 氮於複晶矽與氧化層的界面，因此也改善了複晶矽氧化層的電性。 此外我們更進一步研究熱成長氧化層或沉積的TEOS氧化層於同步磷摻入的複晶矽上之極 性非對稱。此極性非對稱不僅與上下二層複晶矽界面的粗糙度有關，而且與磷在界面的 分佈有關。由此可發現對於同步磷摻入的複晶矽，有較高濃度的磷累積在下層複晶矽與 複晶矽氧化層的界面，但是較低濃度的磷存在於複晶矽氧化層與上層複晶矽的界面，故 使得同步磷摻入比起POCl磷摻入有較大的極性非對稱。另一方面，我們也觀察到即使下 層的複晶矽都是以同步磷的方式摻入，但若上層複晶矽使用POCl3磷摻入會比用同步磷摻 入有較大的磷濃度存在於複晶矽氧化層中。此乃由於高溫的POCl3磷摻入製程會使得大量 的磷擴散進入複晶矽氧化層中，進而劣化複晶矽氧化層的品質。 以快速加熱氮化TEOS化學氣相沉積氧化層結合了氨氣 (NH3) 電漿處理已可應用於複晶矽 薄膜電晶體的閘極電層，此元件呈現了良好的電性以及熱載子可靠性，一般相信乃是由 於氮累積於複晶矽與氧化層的界面且形成了較強之矽氮鍵結，而修補了存在於晶粒中及 通道區域晶界中的損傷鍵結。此外，當溫度或時間增加時，較多的氮釋放出來，薄膜電 晶體的特性也更被改善了。 最後，以氟離子佈植下層的複晶矽而形成的複晶矽氧化層之特性亦被探討。佈植進入的 氟離子在複晶矽氧化層中不僅改善了電特性(如較低的漏電流、較高的崩潰電場)，而且 改善了可靠性 (如較低的電子捕獲率及較大的崩潰電荷量)。此乃由於參與的氟離子能 填補受損傷的鍵結及打斷一些扭曲 (strained) 的矽氧鍵結，而在複晶矽氧化層與複晶 矽界面間形成了強壯的矽氟鍵結。因此氧化層間的局部應力被減輕，並且使得複晶矽與 複晶矽氧化層界面形狀更為平坦，而進一步改善了複晶矽氧化層的品質。

In this thesis, the rapid thermal N2O process for polysilicon oxides and thin -film transistors have been studied. Firstly, we discussed the electrical characteristics of polysilicon oxide grown by using rapid thermal oxidation in N2O (N2O-grown polyoxide), in term of oxidation temperature and thickness with O2-grown polyoxides as comparison. Experimental results showed that a proper amount of nitrogen incorporated in the polyoxide during N2O oxidation can improve the interface of the polysilicon/polyoxide,consequently improving the electrical quality of the N2O-grown polyoxide.However, too much nitrogen release during higher N2O oxidation temperature (1050C) does not improve, instead, degrades the quality of the polyoxide and also causes thick ness non-uniformity. Hence, we presented a 2-step rapid thermal process, i.e. , first oxidation the polysilicon in O2 and then annealing in N2O, which can achieve desired characteristics since proper amount of nitrogen can be incorporated into the polyoxide at the second oxidation step. Then, we presented the TEOS oxide deposited on the phosphorus in-situ doped polysilicon with rapid thermal N2O annealing, which showed good electron trapping characteristic with a large Qbd up to 110 couls/cm2. It was found that the smoother polysilicon/polyoxide interface could be obtained by replacing POCl3 doping with phosphorus in-situ doping and the rapid thermal annealing in N2O.Since the N2O annealing in addition densified the TEOS deposited oxide and incorporated nitrogen into the polyoxide and at the polysilicon/polyoxide interface, thus improving the electrical characteristics. Moreover, we extensively studied the polarity asymmetry of polyoxides grown on the phosphorus in-situ doped polysilicon where the polyoxides were thermally grown oxide or deposited TEOS oxide.The polarity asymmetry is dependent on the interface roughness between the top polysilicon and the bottom polysilicon films, and the phosphorus distribution in the interfaces. It was found that the in-situ doped sample, a higher phosphorus concentration piled up at the bottom polysilicon/polyoxide interface but a lower phosphorus concentration existed in the polyoxide/top polysilicon interface, thus it had larger polarity asymmetry than that of the POCl3 doped sample. We also found that the top polysilicon doped with POCl3 had larger phosphorus concentration in the polyoxide than that with phosphorus in-situ doped even though their bottom polysilicons were all in-situ doped. This was due to that the high temperature POCl3 doping process made larger phosphorus out-diffusion into the polyoxide, thus degraded the polyoxide quality. The TEOS CVD oxides with RTN2O annealing combined with NH3 plasma passivation had been applied as the gate dielectric to the polysilicon thin film transistor (TFT). It was seen that the devices exhibit better electrical characteristics and hot carrier reliability improvements. This was believed due to the nitrogen pile-up at the poly-Si/SiO2 interface and the strong Si-N bond formation, which terminates the dangling bonds in the grains and at the grain boundaries in the channel region. In addition,as the temperature or time was increased, more nitrogen was released. This, furthermore,improved the performances of the TFT. Finally,the characteristics of fluorine-implanted polyoxides were investigated .The implanted-fluorine in the polyoxide did not only improve the electrical characteristics (i.e. lower leakage current and higher electrical breakdown field), but also improved the reliability (i.e. lower electron trapping rate and larger Qbd) of the oxide. This was due to that the incorporated fluorine passivate the dangling bonds and break the strained Si-O-Si bonds to form Si-F bonds in the polyoxide/polysilicon interface. This relaxes the local stress in the oxide network and makes the polysilicon/polyoxide interface morphology more smoother, thus improves the polyoxide quality.