MPEG-II 視訊解壓縮超大型積體電路設計與實現

Abstract

本論文旨在探討第二代視訊壓縮國際標準 MPEG-II 之超大型積體電路之系統設計及實現 策略，以求在符合標準功能規範及效能需求之前提下，追求晶片成本、以及功率消耗之合 理化及最佳化。 在實作上，本論文提出了組成第二代視訊壓縮標準 (MPEG-II at main p rofile and main level) 所需之功能單元設計，這些功能單元包括有可變長度解碼器(Va riable-length decoder)、反離散餘弦單元 (Inverse discrete cosine transform unit )、動態補償單元 (Motion compensation unit) 以及系統控制器 (System controller) 。我們用這些功能單元組成符合 MPEG-II 視訊壓縮規範之超大型積體電路，並實作數位 視訊解壓縮系統。在將視訊功能單元組成解壓縮超大型積體電路系統時，常常需要適當晶 內緩衝記憶體以為輸出入資料流格式轉換所需。另一方面，由於 各功能單元需要存取大 量記憶體以為畫面暫存 (Frame buffer)，實作上多將此記憶體置於解壓縮晶片外以價廉 之動態記憶體 (DRAM) 實現，同時各功能單元共用單一記憶體存取匯流排 (Bus)，以節省 解壓縮晶片腳位，但此組態又使系統需要另一類晶朮緩衝記憶體以調整功能單元及晶外畫 面暫存記憶體之輸出入率。本論文針對此兩類緩衝記憶體提出解析模型，並分析不同晶外 記憶體存取排程方式對晶內緩衝記憶體之影響，用以評估不同功能單元組合下適當之緩衝 記憶體需求，以節省晶片面積。 另一方面基於 MPEG-II 解壓縮器之設計及實作，本論文 亦提出超大型積體電路之設計流程及設計風格，以探討適當之設計方法，並針對設計功能 驗證及晶片測試提出歸納經驗。本論文並提出兩種低功率電路及架構設計策略，以降低 M PEG-II 解壓縮器功能單元及記憶體匯流排功率消耗。前者利用可變長度編解碼器位元平 移量之可忽略性，而後者利用匯流排位元編碼方式，以減少位元切換次數。兩者可有效降 低 22% 至 50% 之功率消耗。

This dissertation explores the design and implementation issues of decompressi on VLSI for ISO/IEC MPEG-II video compression standard. It proposes systematic strategies to optimize the cost and power dissipation under the function and performance requirements specified by MPEG-II video compression standard.This dissertation first presents the design of video decoder VLSI for main profile and main level of MPEG-II video compression standard. This decoder consists of several functional units that implement the building blocks for the decoding of compressed MPEG-II video. These functional units include the variable-lengt h decoder (VLD), the discrete consine transform unit (IDCT) and the motion com pensation unit (MC). The decoding process is controlled by a RISC-style system controller. A video decompression system is also constructed with the impleme ntation of MPEG-II decoder VLSI. In order to construct the VLSI system with fu nctional units, there frequently needs on-chip buffer inserted between functio nal units for format conversion. For MPEG-II video decompression, furthermore, it is necessary for functional units to access a large capacity of storage, w hich is frequently implemented off the decoder chip with low cost DRAM, for fr ame bufferring. The functional units thus may have to access the off-chip fram e buffer via a shared common bus for saving the chip pin count. Nevertheless, this configuration introduces the necessity of another kind of on-chip buffer between functional unit and off-chip memory for rate adaptation. For these two classes of on-chip buffers, this dissertation proposes an analytical model to estimate the requirements of on-chip buffers for different functional units. Also, it explores the impact of different bus access scheduling strategies on the on-chip buffer. These results can be used to optimize the on-chip buffer s ize for MPEG-II video decoder VLSI.Based on the design and implementation of t he MPEG-II video decoder VLSI, this dissertation will present the preferred de sign styles and explores the VLSI design methodology. Also, this dissertation summaries the experiences of software simulation, hardware emulation and DFT ( design for testability) for design verification. Finally, this dissertation pr oposes two circuit-level and architectural-level power reduction techniques to minimize the power dissipation of the MPEG-II video decoder. One of them is t o make the barrel shifter in the variable-length decoder to turn off the unnec essary shifting bits, while the other one is to use bit encoding strategy to i ncrease the data correlation on the memory bus. Both strategies can effectivel y reduce the number of bit switches and thus reduce the power dissipation up t o 50\% and 22\%, respectively.