标题: | MPEG-II 视讯解压缩超大型积体电路设计与实现 Design and Implementation of MPEG-II Video Decoder VLSI |
作者: | 林嘉兴 Lin Chia-Hsing 任建葳 Chein-Wei Jen 电子研究所 |
关键字: | 超大型积体电路;解压缩器;视讯压缩;VLSI;video decoder;video compression |
公开日期: | 1998 |
摘要: | 本论文旨在探讨第二代视讯压缩国际标准 MPEG-II 之超大型积体电路之系统设计及实现 策略,以求在符合标准功能规范及效能需求之前提下,追求晶片成本、以及功率消耗之合 理化及最佳化。 在实作上,本论文提出了组成第二代视讯压缩标准 (MPEG-II at main p rofile and main level) 所需之功能单元设计,这些功能单元包括有可变长度解码器(Va riable-length decoder)、反离散余弦单元 (Inverse discrete cosine transform unit )、动态补偿单元 (Motion compensation unit) 以及系统控制器 (System controller) 。我们用这些功能单元组成符合 MPEG-II 视讯压缩规范之超大型积体电路,并实作数位 视讯解压缩系统。在将视讯功能单元组成解压缩超大型积体电路系统时,常常需要适当晶 内缓冲记忆体以为输出入资料流格式转换所需。另一方面,由于 各功能单元需要存取大 量记忆体以为画面暂存 (Frame buffer),实作上多将此记忆体置于解压缩晶片外以价廉 之动态记忆体 (DRAM) 实现,同时各功能单元共用单一记忆体存取汇流排 (Bus),以节省 解压缩晶片脚位,但此组态又使系统需要另一类晶术缓冲记忆体以调整功能单元及晶外画 面暂存记忆体之输出入率。本论文针对此两类缓冲记忆体提出解析模型,并分析不同晶外 记忆体存取排程方式对晶内缓冲记忆体之影响,用以评估不同功能单元组合下适当之缓冲 记忆体需求,以节省晶片面积。 另一方面基于 MPEG-II 解压缩器之设计及实作,本论文 亦提出超大型积体电路之设计流程及设计风格,以探讨适当之设计方法,并针对设计功能 验证及晶片测试提出归纳经验。本论文并提出两种低功率电路及架构设计策略,以降低 M PEG-II 解压缩器功能单元及记忆体汇流排功率消耗。前者利用可变长度编解码器位元平 移量之可忽略性,而后者利用汇流排位元编码方式,以减少位元切换次数。两者可有效降 低 22% 至 50% 之功率消耗。 This dissertation explores the design and implementation issues of decompressi on VLSI for ISO/IEC MPEG-II video compression standard. It proposes systematic strategies to optimize the cost and power dissipation under the function and performance requirements specified by MPEG-II video compression standard.This dissertation first presents the design of video decoder VLSI for main profile and main level of MPEG-II video compression standard. This decoder consists of several functional units that implement the building blocks for the decoding of compressed MPEG-II video. These functional units include the variable-lengt h decoder (VLD), the discrete consine transform unit (IDCT) and the motion com pensation unit (MC). The decoding process is controlled by a RISC-style system controller. A video decompression system is also constructed with the impleme ntation of MPEG-II decoder VLSI. In order to construct the VLSI system with fu nctional units, there frequently needs on-chip buffer inserted between functio nal units for format conversion. For MPEG-II video decompression, furthermore, it is necessary for functional units to access a large capacity of storage, w hich is frequently implemented off the decoder chip with low cost DRAM, for fr ame bufferring. The functional units thus may have to access the off-chip fram e buffer via a shared common bus for saving the chip pin count. Nevertheless, this configuration introduces the necessity of another kind of on-chip buffer between functional unit and off-chip memory for rate adaptation. For these two classes of on-chip buffers, this dissertation proposes an analytical model to estimate the requirements of on-chip buffers for different functional units. Also, it explores the impact of different bus access scheduling strategies on the on-chip buffer. These results can be used to optimize the on-chip buffer s ize for MPEG-II video decoder VLSI.Based on the design and implementation of t he MPEG-II video decoder VLSI, this dissertation will present the preferred de sign styles and explores the VLSI design methodology. Also, this dissertation summaries the experiences of software simulation, hardware emulation and DFT ( design for testability) for design verification. Finally, this dissertation pr oposes two circuit-level and architectural-level power reduction techniques to minimize the power dissipation of the MPEG-II video decoder. One of them is t o make the barrel shifter in the variable-length decoder to turn off the unnec essary shifting bits, while the other one is to use bit encoding strategy to i ncrease the data correlation on the memory bus. Both strategies can effectivel y reduce the number of bit switches and thus reduce the power dissipation up t o 50\% and 22\%, respectively. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT870428004 http://hdl.handle.net/11536/64284 |
显示于类别: | Thesis |