完整後設資料紀錄
DC 欄位語言
dc.contributor.author謝建興en_US
dc.contributor.authorJiann-Shing Shiehen_US
dc.contributor.author沈文仁en_US
dc.contributor.authorWen-Zen Shenen_US
dc.date.accessioned2014-12-12T02:20:39Z-
dc.date.available2014-12-12T02:20:39Z-
dc.date.issued1998en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT870428013en_US
dc.identifier.urihttp://hdl.handle.net/11536/64294-
dc.description.abstract在電路設計時,為了達成高速及低功率是必要的,在不會造成速度減慢的前題下,對於降低功率而言,同時減低電源電壓及臨界電壓是有效的. 但它會引入一些問題,如漏電功率的大量增加. 為了要克服此一問題,有許多方法被提出,經歸納有三種方式:1) 利用多種臨界電壓 2)透過基底偏壓控制臨界電壓 3)兼具以上二者另外,SOI CMOS 的技術也將被討論. 在此論文中,我們提出一個改良的低功率/低電壓正反器電路(可減小clk振幅)在主動/待命模式的應用,並與其他正反器比較. 這個改良的正反器是由低臨界電壓組成,並且串接高臨界電壓 cut-off MOSs, 另外SRAM 單元也加入這改良的正反器中. 這6T SRAM能在待命模式下儲存資料. 6T SRAM儲存單元是由高臨界電壓MOSs組成,是為了要抑制待命模式下的漏電流. 最後,我們採用上述改良的電路來設計並行、低功率、高速度管線式乘法器. 在架構上、電路設計上、平面佈局上、以及連線上,我們均以低功率、高速為設計重心,並將這些技術應用到16*16位元以及32*32位元的乘法器上,從模擬的結果來看,在功率及速度的性能上均能達到預期的成果.zh_TW
dc.description.abstractIt is well known that scaling down both the supply voltage and threshold voltage is effective in reducing the power consumption while maintaining the high operation speed. However, it induces some problems, for instance, the standby power is increased dramatically. In order to cope with the problem, several circuit schemes are proposed. We classify those schemes into 3 classes: 1) Multiple Threshold voltage(MTCMOS) 2) Variable Threshold voltage with substrate bias controlling (VTCMOS) 3) combined MTCMOS and VTCMOS(MVCMOS). In addition, Silicon on Insulator (SOI) based technology is also discussed. In this thesis, we also proposed an improved RCSFF (Reduced Clock Swing Flip-Flop) circuit design which is applicable to both active and standby mode. The improved flip-flop is made of low-Vth devices to achieve high speed with serial cut-off high Vth MOSs. 6T SRAM cell is added to the flip-flop to hold the latched data in the standby mode. The 6T SRAM storage element is composed of high-Vth MOSs to suppress leakage current in standby mode. Finally, we adopted the improved RCSFF(Reduced Clock Swing Flip-Flop) circuit to design parallel, low power, high speed, and 2-stage pipelined multipliers with Modified Booth algorithm. From the architecture design, circuit design to floor plan and routing, high speed and low power consumption are our design guidelines. 16*16 bits and 32*32 bits multipliers are implemented to demonstrate the effectiveness of our techniques. From our simulation results, the low power consumption and high operation speed do achieve our expectation.en_US
dc.language.isoen_USen_US
dc.subject多臨界電壓zh_TW
dc.subject低電壓/低功率zh_TW
dc.subject乘法器zh_TW
dc.subject主動/待命zh_TW
dc.subject漏電流zh_TW
dc.subjectMTCMOSen_US
dc.subjectLow Voltage/Low Poweren_US
dc.subjectmultiplieren_US
dc.subjectactive/standbyen_US
dc.subjectleakageen_US
dc.title一個改良的低電壓/低功率CMOS數位電路設計zh_TW
dc.titleAn Improved Low Voltage/Low Power Multi-Threshold CMOS Digital Circuit Designen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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