階層式障礙模型與其測試圖樣之產生

Abstract

階層式的處理方法通常被使用於大型電路系統的分析和設計。在此論文中，我們提出了階層式的障礙模型，與依據此模型所產生之測試圖樣。首先、我們分析在電晶體階層的元件障礙，以建構開迴路運算放大器的轉移函數模型，然後、另一個閉回路運算放大器階層的轉移函數模型可利用開回路放大器階層的轉移函數模型推導出來，我們亦可用此模型推導出更高階系統的障礙模型，以一個state-variable 濾波器作例子。各階層參數間的關係會被推導出來，依據被推導出來的障礙模型，偵測障礙的測試圖樣亦被推導出來。

"Hierarchy" approach is usually used either in analysis or design large scale system. In this thesis, we propose a hierarchical fault model and test pattern generation based on this model. At first, a transfer function model for an open-loop operational amplifier (OP) is presented based on analysis of element faults at the transistor level. Then another transfer function model is presented based on the derived open-loop OP level for the closed-loop OP level. This model is then used again to derive the higher level fault model for a system, for which a state-variable benchmark filter is used as an example. The relationships of parameters between each level are derived. Based on the derived fault model, test patterns to detect faults are derived.