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dc.contributor.author黃英兆en_US
dc.contributor.authorYin-Chao Huangen_US
dc.contributor.author李崇仁en_US
dc.contributor.authorProf. Chung-Len Leeen_US
dc.date.accessioned2014-12-12T02:20:49Z-
dc.date.available2014-12-12T02:20:49Z-
dc.date.issued1998en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT870428085en_US
dc.identifier.urihttp://hdl.handle.net/11536/64373-
dc.description.abstract階層式的處理方法通常被使用於大型電路系統的分析和設計。在此論文中,我們提出了階層式的障礙模型,與依據此模型所產生之測試圖樣。首先、我們分析在電晶體階層的元件障礙,以建構開迴路運算放大器的轉移函數模型,然後、另一個閉回路運算放大器階層的轉移函數模型可利用開回路放大器階層的轉移函數模型推導出來,我們亦可用此模型推導出更高階系統的障礙模型,以一個state-variable 濾波器作例子。各階層參數間的關係會被推導出來,依據被推導出來的障礙模型,偵測障礙的測試圖樣亦被推導出來。zh_TW
dc.description.abstract"Hierarchy" approach is usually used either in analysis or design large scale system. In this thesis, we propose a hierarchical fault model and test pattern generation based on this model. At first, a transfer function model for an open-loop operational amplifier (OP) is presented based on analysis of element faults at the transistor level. Then another transfer function model is presented based on the derived open-loop OP level for the closed-loop OP level. This model is then used again to derive the higher level fault model for a system, for which a state-variable benchmark filter is used as an example. The relationships of parameters between each level are derived. Based on the derived fault model, test patterns to detect faults are derived.en_US
dc.language.isozh_TWen_US
dc.subject障礙模型zh_TW
dc.subject階層zh_TW
dc.subject類比測試zh_TW
dc.subject測試圖樣產生法zh_TW
dc.subjectfault modelen_US
dc.subjectHierarchicalen_US
dc.subjectanalog testingen_US
dc.subjecttest pattern generationen_US
dc.title階層式障礙模型與其測試圖樣之產生zh_TW
dc.titleHierarchical Fault Model and Its Test Pattern Generationen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
顯示於類別:畢業論文