選擇性液相沈積技術在VLSI製程之應用與研發

Abstract

元件接觸孔之製作是一項足以決定元件特性的關鍵製程。基於非等向性蝕刻能力之考量，過去都是採用活性離子蝕刻法來製作接觸孔。在本論文中，我們首先開發出一種可用於取代活性離子蝕刻的技術--選擇性液相沈積法，來製作元件接觸孔，並用此來解決許多採離子蝕刻所會產生的問題。 在初步的應用中，相較於活性離子蝕刻，接觸孔改採選擇性液向沈積法製作之n+/p二極體具有較低之逆偏電流、較趨於1之理想因子、較高之順偏電流、較低之接觸電阻，以及對熱有較高之穩定性等優點。同樣我們進一步探討此種可使表面無電漿損傷的技術，應用於肖特基二極體、超淺接面二極體時之優點。而逆偏高溫劣化法測試之結果顯示此接觸孔具有令人滿意之信賴性。我們的實驗結果說明了選擇性液相沈積法不僅具備如活性離子蝕刻般製作次微米尺寸接觸孔的能力，同時可改善元件，使之能具有如濕式蝕刻所得之元件一般之良好特性。 再來我們著重於探討將選擇性液相沈積法，應用於金氧半場效電晶體源極汲極接觸孔之製作。同樣地，採選擇性液相沈積法所製作之電晶體具有較理想之次臨限變動、較低之閉電流、較大之汲極飽和電流、以及較高之場效遷移率等，這可歸因於電晶體中通道矽-氧化矽界面缺陷、n+/p 接面逆偏漏電、以及接觸電阻等之明顯改善。這些優點證實了選擇性液相沈積法可取代離子蝕刻，用以製作高效能元件。之後我們採熱載子劣化法，以及Fowler-Nordham (F-N)劣化法來驗證電晶體之信賴性，結果發現因矽-氧化矽界面弱鍵結所引發之缺陷電荷較少，選擇性液相沈積法所得元件之劣化程度顯得較為輕微。 接著我們評估比較由液相沈積氧化矽覆蓋，以及傳統電漿輔助TEOS化學氣相沈積氧化矽所覆蓋之元件特性。液相沈積覆蓋之大多數元件特性，諸如遷移率、次臨限變動等，都較電漿輔助沈積覆蓋者為佳，尤其可保有較低之閘極氧化層漏電流和閘極引發汲極漏電流，但對於F-N劣化之抵抗能力卻變弱。這些結果我們認為是因為液相沈積氧化矽中所含之氟可鈍化氧化矽-矽介面之危鍵結，同時此法免除了電漿輔助沈積時所產生位於閘極汲極之n+重疊區域之缺陷電荷產生，但氟卻也降低了對劣化測試之抵抗力。 另外我們嘗試將選擇性液相沈積法應用於製作溝型隔絕。實驗結果顯示，以此法所得到之淺溝來製作各種元件都能具有令人滿意的電特性。另外我們進一步發現，因選擇性液相沈積法的絕佳保角覆蓋能力，可將其氧化矽填入具高外觀比的深溝結構中，而無任何空洞發生。最後總而言之，採用選擇性液相沈積法製作之接觸孔可改善絕大多數的元件特性，本論文之結果證實了選擇性液相沈積在VLSI製程中確是一項極有價值的技術，因為沒有電漿損傷和污染，尤其可以用來取代傳統之活性離子蝕刻製作高品質之接觸孔。

The contact hole formation is an important issue which severely affects the performance of devices. The general method to form contact holes is using reactive ion etching (RIE) due to its ability of anisotropic etching. In this thesis, we at first develop an alternative method, selective liquid-phase deposition (S-LPD), to fabricate contact holes, and apply it to solving the drawbacks caused by RIE. In preliminary applications, the n+/p junction diodes with contact holes prepared by S-LPD exhibit much less reverse current, unity ideality factor, larger forward current, lower contact resistance and higher thermal stability than those prepared by RIE. Further superiority of plasma damage-free on near-surface regions is also investigated through the Schottky & ultra-shallow junction diodes. The data after reverse bias temperature stress (RBTS) indicates the satisfactory reliability of S-LPD contact holes. These results reveal that S-LPD not only can form contact holes with submicron meter scale as RIE used, but also can promote the device performance comparable to wet etching. This work subsequently emphasizes on the application of S-LPD to the contact hole formation of MOSFETs instead of RIE. Similarly due to plasma-free, the MOSFETs fabricated by S-LPD can exhibit more ideal subthreshold swing, lower off-current, larger saturated drain current and higher field-effect mobility than those fabricated by RIE. This can be attributed to the significant improvements on the SiO2/Si interface traps at MOSFETs’ channels, the n+/p junction leakage and the contact resistance. These advantages confirm that S-LPD can be used for replacing RIE in the fabrication of high performance devices. The hot carrier stress and Fowler-Nordham stress are employed to clarify the reliability of S-LPD devices. The stress degradations can be alleviated due to less trap charges generated via weak bonds at SiO2/Si interface in S-LPD devices. Next, we compare and evaluate the performance of devices capped with LPD and PE-TEOS oxide, respectively. Most of the characteristics, such as mobility and swing, of LPD samples are better than those of PE-TEOS samples. The LPD devices especially keep gate leakage and gate-induced drain leakage (GIDL) to be rather low. However, the degradation by F-N stress is more serious than PE-TEOS devices. It is attributed to that fluorine passivates the dangling bonds at SiO2/Si interface, and LPD capping avoids the traps charged by PECVD plasma and locating at the n+ overlap region between gate and source/drain, but fluorine-contained makes the stress immunity worse. Finally, we transfer to develop an another application of S-LPD to the trench isolation formation. Experimental results show that the devices and MOSFETs isolated with S-LPD shallow trenches can exhibit satisfactory I-V performance. It is further found that S-LPD can refill oxide without void into the deep trenches with high aspect-ratio due to its ultra conformal coverage. In conclusion, almost all characteristics of devices can be improved by means of utilizing S-LPD contact holes. Results in this thesis demonstrate that S-LPD is indeed a highly promising technology in VLSI process, especially in replacing RIE process to form high-quality contact holes owing to damage free and contamination free nature.