效能最佳化公式之推導及其於以連線為導向平面規劃之應用

Abstract

當製程技術演進到了深次微米的紀元，連線問題擔任起決定電路效能的支配角色。擺放緩衝器/改變緩衝器形狀（buffer insertion/sizing）以及改變導線形狀（wire sizing）是最有效而且最普遍使用來減低導線延遲的技術，而且是傳統中被應用在後段佈局（post-layout）的最佳化技術。根據半導體工業協會（SIA）技術準則的預測，然而，在一個晶片裡面不同區塊之間的連線數量、以及擺放用來作效能最佳化的緩衝器數量將會有引人注目的增加。很明顯地，在後段佈局時，當大部分的繞線空間都已經被佔據了的時候，要擺放以及改變數十萬個緩衝器是不可行的。因此，將緩衝器區塊（buffer block）以及導線形狀規劃與平面規劃合併變成不可或缺的。在這篇論文當中，我們首先以更精確的模式導出連續的擺放緩衝器/改變緩衝器形狀（buffer insertion/sizing）以及改變導線形狀（wire sizing）的性能最佳化公式，然後將這公式應用到同時考慮緩衝器區塊規劃以及考慮導線形狀規劃的連線為導向平面規劃（interconnect-driven floorplanning）。實驗結果顯示，我們的研究可以讓90%的導線符合它們的時間限制，而且只使用了比原本平面規劃多出0.5%的面積來擺放緩衝器以及改變導線形狀，分別跟[9]和[20]中66%和85%的導線符合它們的時間限制、以及多耗費了1.1%和1.3%的面積來比較。

As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are the most effective and popular techniques to reduce interconnect delay and are traditionally applied to post-layout optimization. As the SIA technology roadmap predicts, however, the number of interconnections among different blocks and that of buffers inserted in a chip for performance optimization will grow dramatically [22, 23]. It is obviously infeasible to insert/size hundreds of thousands buffers or wires during the post-layout stage when most routing regions are occupied. Therefore, it is critical to incorporate buffer-block and wire-size planning into floorplanning to ensure timing closure and design convergence. In this paper, we first derive continuous buffer insertion/sizing and wire sizing formulae for performance optimization under a more accurate wire model, and then apply the formulae to interconnect-driven floorplanning that considers not only the buffer-block planning addressed in [9], but also wire-size planning. Experimental results show that our approaches achieve an average success rate of 90% of nets meeting timing constraints and consume an average extra area of only 0.5% over the given floorplan, compared with the average success rates of 66% and 85% and extra areas of 1.1% and 1.3% resulted from recent works in [9] and [20], respectively.