MPEG-II 視訊解碼智產之虛擬原型

Abstract

在系統複雜度愈形提高，但產品開發時間卻越來越短的情形下，虛擬原型成為系統設計中不可或缺的要件。採用虛擬原型將使得整個系統的設計及驗證得以及早進行，使系統整合更加順利。 在本論文中，我們提出一個MPEG-II視訊解碼智產的虛擬原型以及虛擬原型設計方法。我們採用以C/C++為基礎的平台SystemC來建構我們的虛擬原型，因此可以達到高模擬速度，並且可以有效率地進行不同的效能評估。此外，我們也在論文說明了由既有的程式碼轉換為虛擬原型的過程。

For development of complex systems with a shrinking design time, virtual prototyping is essential for an efficient design process. A virtual prototyping environment allows the design and verification of complete systems, from functional and performance constraints to system integration. We describe a virtual prototype of an MPEG-II video decoder IP and its design methodology in this thesis. Our virtual prototyping environment is constructed with SystemC, a C/C++ based modeling platform. Therefore, our full functional virtual prototype can process about one frame of MPEG-II compressed video per minute. This allows us to measure different performance metrics and make system design tradeoffs efficiently. The design process of transform existing program to virtual prototype simulation models is also discussed. 1.1 TYPICAL SYSTEM DESIGN FLOW 1.2 VERIFICATION BOTTLENECK 1.3 THESIS ORGANIZATION CHAPTER 2 SYSTEM LEVEL DESIGN AND VIRTUAL PROTOTYPES 2.1 DEFINITION OF VIRTUAL PROTOTYPE 2.2 BENEFITS OF USING VIRTUAL PROTOTYPES 2.3 SYSTEM LEVEL DESIGN LANGUAGES CHAPTER 3 VIRTUAL PROTOTYPE IMPLEMENTATION 3.1 SYSTEMC MODELING PLATFORM 3.1.1 Executable Specification and the SystemC Library 3.1.2 Overview of the SystemC Design Flow 3.1.3 Features of the SystemC Class Library 3.1.4 Summary 3.2 VIRTUAL PROTOTYPE DESIGN FLOW 3.2.1 Functionality Partition 3.2.2 Module Specification 3.2.3 Communication Refinements CHAPTER 4 AN MPEG-II VIDEO DECODER IP 4.1 THE IP OVERVIEW 4.1.1 MPEG-II I/O 4.1.2 Functional Blocks in MPEG-II IP 4.1.3 IP Design Issues 4.2 SIMULATION TESTBENCH 4.2.1 System Testbench Overview 4.2.2 The Host Model 4.2.3 The RAM Model 4.2.4 The Bus Arbiter 4.3 SIMULATION RESULTS CHAPTER 5 CONCLUSIONS AND FUTURE WORK BIBLIOGRAPHY