以準分子雷射結晶方法製作高性能低溫複晶矽薄膜電晶體之研究

Abstract

本研究提出了一種新的雷射結晶方法，以及兩種元件結構，使低溫複晶矽薄膜電晶體有高效能的特性表現。 低溫複晶矽薄膜電晶體多被運用於主動式陣列顯示器(active matrix displays)的開關元件(switching devices)以及在其同一基板上的周邊控制電路。而高性能的複晶矽薄膜電晶體也有機會用在垂直整合(vertical integration)的超大型積體電路上，如此一來除了可使整體的集成密度提升更可藉由減少信號傳輸的延遲而增加積體電路的效能。為了達到這個目標，就必須使用低溫且高品質的製程方法。為求讓製程低溫且有高品質的結果，使用製程熱預算低的準分子雷射(excimer laser)來結晶矽薄膜或活化摻雜物將是最好的選擇。然而，製程結果的不一致以及製程可容忍變異的範圍太狹窄，有時反而掩蓋了準分子雷射製程原有的優點，使得製作結果與原有的預期有所差異。 在論文中，我們展示一種新的製作方式用來改善所面臨的問題。這種方式是使用準分子雷射照射並搭配凹陷的矽薄膜結構，如此當雷射照射時，我們可以刻意讓薄的區域其整層膜完全被熔融，而較厚的區域被熔融的深度較淺。這樣的熔融方式可以迫使結晶從較厚的區域開始，然後伸入膜較薄的區域。我們透過掃描式電子顯微鏡的觀察發現在凹陷區較短的結構中，晶粒可以延伸長達1.5微米。這種結晶方法不但可以控制晶粒的位置，更可擴大製程可以容忍的變異範圍。這是因為，若要達到薄的區域整層膜完全被熔融，而較厚的區域被熔融的深度較淺，此時雷射能量只要大於某個值讓薄的(凹陷的)區域得以完全熔融即可。 我們用上述的雷射結晶方法來製作複晶矽薄膜電晶體，且設計讓通道(channel)的部分位於凹陷處，而源極(source)和洩極(drain)位在較厚的兩旁。由於在凹陷的通道區上是橫向成長的晶粒所在之處，使得整體的電性包括載子移動率(mobility)、subthreshold swing、開關電流比(on-off current ratio)和漏電流(leakage current)等，都有極佳的表現。尤其是元件的通道越短，電性表現越好。因為短通道的元件中，最終只會有兩顆晶粒在通道上。因此在通道為1微米的元件都有像單晶元件般載子移動率超過500 cm2/V.s的性質。此外，我們發現若將閘極(gate)涵蓋到厚的矽膜區域，此時將可製造出洩極接面(drain junction)較深的元件。由於洩集接面較深，可以削弱側向電場，因此元件的kink效應減低了，且有較強健的熱載子穩定度。 除了以上所提及的，為了改良元件的特性，我們製作一種對稱的self-aligned graded LDD (SAGLDD)薄膜電晶體。我運用補償結構(offset)作離子佈植以及雷射的照射來製作此結構。不同於一般傳統的LDD結構的製作方式，SAGLDD薄膜電晶體不需要額外的微影製程、或spacer的製作以及兩次的離子佈植來作出兩種不同的摻雜濃度。更重要的是，我們由計算得知以這種方式製作的漸層(graded) LDD其串聯電阻為一般LDD結構的十分之一。因此我們由元件的特性曲線可看出，這種LDD結構可減低漏電流，但對導通電流(on current)卻影響不大。

Low-temperature poly-Si thin-film transistors (LTPS TFTs) have been used as pixel switches in active matrix displays and as devices in driver integration onto display substrate as well. High-performance poly-Si TFTs may allow the vertical integration of devices for VLSI that can increase packing density and improve performance through reduced interconnect delay. To attain this goal, we should use low-temperature fabrication methods to produce high-quality device performance. For the sake of low-temperature process and high-quality results, using excimer laser for crystallization of silicon thin films and activation of dopants seems to be the best choice for device fabrication with low thermal-process budget. Unfortunately, poor uniformity and narrow process window of excimer laser crystallization (ELC) process sometimes smothers its merit, and disappoint our expectation. In this thesis, we demonstrate a novel process that is able to overcome the mentioned problems by using excimer laser accompanying with recess-structured silicon films. We use this method to create complete melting in thin regions but partial melting in thick regions of silicon films during laser irradiation. This melting process forces crystallization to commence from the thick films to the thin. Especially when the recessed regions become shorter, the extending grains that have been observed using SEM can stretch to about 1.5µm. Hence, by using this method, we can control grain growth in the recessed regions as well as broaden the process window. The reason is that if the laser energy density is over a level that can completely melt the thin, recessed regions, lateral grain growth will occur. We use this process to fabricate recessed-channel TFTs (RCTFTs) having thin channels and thick sources/drains. Since the channel regions are located with well-crystallized longitudinal grains, the device performance, such as field-effect mobility, subthreshold swing, on-off current ratio and leakage current, is excellent. The performance is getting better when the channel length becomes shorter because the small devices will finally contain only two grains in their channels. The 1-µm RCTFTs even show single-crystal-SOI-like electrical characteristics with high mobility that is greater than 500 cm2/V.s. Furthermore, we find that the RCTFTs with thick drain junctions possessing weaker lateral electric field are capable of alleviating kink effect, and also have robust hot-carrier reliability. In addition, to improve device performance, we fabricate the TFTs with symmetric self-aligned graded lightly doped drain (SAGLDD). The method contains an offset ion implantation and excimer laser irradiation. Unlike conditional LDD structure, the SAGLDD can be fabricated without additional lithography, spacer forming or extra ion implantation to construct junctions that contain two different doping concentrations. Most importantly, we have proved that the series resistance of graded LDD structure is about one order lower than that of the conventional LDD structure. Therefore, SAGLDD TFTs exhibit less leakage current without diminishing on current comparing with the conventional self-aligned TFTs. By using the proposed process method, ELC with recess-structured a-Si films, and device structures, RCTFTs and symmetric SAGLDD TFTs, we have enabled the fabrication of high-performance low-temperature TFTs. ABSTRACT III 謝 誌 V TABLE LISTS IX FIGURE CAPTIONS X CHAPTER 1: INTRODUCTION 1 1.1 Overview of Low-Temperature Polycrystalline Silicon Thin-Film Transistors (LTPS TFT) 1 1.2 Overview of Methods for Preparing Polycrystalline Silicon Thin Films 2 1.3 Motivation 3 1.3.1 Channel engineering – 4 1.3.2 Drain engineering 1 -- Alleviate kink effect (floating body effect) in LTPS TFTs without LDD 4 1.3.3 Drain engineering 2 – Alleviate kink effect (floating body effect) in LTPS TFTs with symmetric self-aligned graded lightly doped drain (SAGLDD) 5 1.4 Thesis Outline 5 CHAPTER 2: EXCIMER LASER CRYSTALLIZATION OF AMORPHOUS SILICON THIN FILMS 7 2.1 INTRODUCTION 7 2.2 EXPERIMENTAL PROCEDURE 10 2.3 RESULTS AND DISCUSSION 11 2.3.1 Optical properties of the ELC polysilicon films 11 2.3.2 Observation of grain configuration in ELC polysilicon films using SEM 15 2.4 SUMMARY 18 CHAPTER 3: PHOTO-THERMAL DESIGN FOR EXCIMER LASER CRYSTALLIZATION OF AMORPHOUS SILICON THIN FILMS 19 3.3 EXPERIMENTAL PROCEDURE 28 3.4 THEORETICAL DISCUSSION 29 3.4.1 Control of localized thermal gradient with different thicknesses of α-Si thin film 29 3.4.2 Control of Different Energy Density Absorbed by Selected Regions in □-Si thin film 38 3.5 RESULTS AND EXPERIMENTAL DISCUSSION 42 3.5.1 Control of Localized Thermal Gradient with Different Thicknesses in α-Si thin film 42 3.5.2 Control of grain growth with combination of recess-structured silicon film and reflective/antireflective capping layers 47 3.6 SUMMARY 49 CHAPTER 4: ELECTRICAL CHARACTERISTICS OF ELC RECESSED-CHANNEL TFTS (RCTFTS) 51 4.1 INTRODUCTION 51 4.2 EXPERIMENTAL PROCEDURE 53 4.3 RESULTS AND DISCUSSION 56 4.3.1 Uniformity and performance of conventional TFTs and RCTFTs 56 4.3.2 RCTFTs with thin and thick drain junctions 64 4.4 SUMMARY 71 CHAPTER 5: SYMMETRIC SELF-ALIGNED GRADED LIGHTLY DOPED DRAIN (SAGLDD) TFTS 72 5.1 INTRODUCTION 72 5.2 EXPERIMENTAL PROCEDURE 73 5.3 RESULTS AND DISCUSIONS 75 5.3.1 Device performance 75 5.3.2 Reliability issue 81 5.4 SUMMARY 83 CHAPTER 6: CONCLUSIONS 84 REFERENCES 87 Chapter 1 87 Chapter 2 89 Chapter 3 91 Chapter 4 93 Chapter 5 94 簡 歷 96