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dc.contributor.author陳建亨en_US
dc.contributor.authorJiann Heng Chenen_US
dc.contributor.author雷添福en_US
dc.contributor.author趙天生en_US
dc.contributor.authorTan Fu Leien_US
dc.contributor.authorTien Sheng Chaoen_US
dc.date.accessioned2014-12-12T02:23:20Z-
dc.date.available2014-12-12T02:23:20Z-
dc.date.issued1999en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT880428125en_US
dc.identifier.urihttp://hdl.handle.net/11536/65770-
dc.description.abstract本論文主要是研究以氫氟酸氣態清洗及氮摻雜之閘極氧化層與複晶矽氧化層的特性。首先,要製作一個無自然氧化層(native-oxide-free)之表面,使用不同接觸孔徑(contact hole)的清洗方式來比較傳統的濕式液態氫氟酸(conventional wet HF)與新式同步氫氟酸氣態清洗(in-situ HF vapor cleaning)的不同。利用密集式(cluster)同步氣態氫氟酸處理與同步摻雜(in-situ doped)複晶矽沉積製程可避免試片曝露在大氣中,複晶矽栓塞(poly-plug)結構的源極/汲極(source/drain)之接觸電阻(contact resistance)可明顯下降。此外,我們並試作了一個使用超薄閘極氧化層(ultra-thin gate oxide)的深次微米n型金氧半電晶體(deep-submicron n-MOSFETs)。 這個外加的同步氫氟酸氣態清洗可減少自然氧化層的再生長(re-growth)並改善晶片的表面粗糙度(surface roughness)。我們的結果顯示無自然氧化層(native-oxide-free)之4 nm超薄閘極氧化層的漏電流、表面能態(interface states),n型金氧半電晶體元件的汲極電流(Id)與通道電導(Gm)、 SILC (stress-induced leakage current)與熱載子(hot carrier)抵抗力都有明顯改善。 我們還結合氮離子在閘極的佈植(nitrogen gate electrode implantation)與同步氫氟酸氣態清洗來製作使用超薄閘極氧化層的深次微米n型金氧半電晶體。結果顯示4 nm超薄閘極氧化層的漏電流、Qbd(charge-to-breakdown)、表面能態(interface states),n型金氧半電晶體元件的汲極電流(Id)與通道電導(Gm)、Icp(charge pumping current)、 SILC (stress-induced leakage current)與熱載子(hot carrier)抵抗力都有明顯改善。這些性能與穩定度的改善主要歸因於結合同步氫氟酸氣態清洗與氮離子在閘極的佈植所帶來的無自然氧化層製程、平坦的表面、氮摻雜與在介面上較少的砷(As)摻雜。 我們提出結合N2O氮化處理(nitridation)與化學機械研磨製程 (CMP, Chemical Mechanical Polishing)的方法來成長高品質的複晶矽氧化層。並利用AFM 與 TEM觀察複晶矽氧化層/複晶矽介面的粗糙與平整度,SIMS來分析磷(phosphorous)與氮(nitrogen)的縱深分佈。實驗結果顯示,與非CMP (Non-CMP)的試片相比,在經化學機械研磨製程拋光後複晶矽表面成長的氧化層有低漏電流、高介電質崩潰電場(dielectric breakdown field)、高電子能障(electron barrier height)、低電子捕捉率(electron trapping rate)、高Qbd (charge-to-breakdown)與低捕捉電荷密度(density of trapping charge)的極佳特性。再者,化學機械研磨製程增加了N2O氮化處理時氮原子在介面間的摻雜而進一步增進了複晶矽氧化層的品質。此外,經化學機械研磨製程改善的複晶矽的表面也減少了在熱成長過程中磷原子(phosphorous)的向外擴散(out-diffusion)。 更進一步的,我們也結合化學機械研磨製程與N2/N2O高溫加熱退火(RTA)來增進LPCVD TEOS複晶矽氧化層的特性。此法製備的TEOS複晶矽氧化層有較佳之J-E曲線、較高的Qbd (charge-to-breakdown)與低電子捕捉率(electron trapping rate)。經不同溫度下N2O退火的TEOS複晶矽氧化層特性也必須研究。這種雙層的結構 (TEOS 沉積與RTA熱成長氧化層),讓複晶矽氧化層在不同電注入(+Vg and –Vg injection) 方向,在漏電流、電子捕捉率(electron trapping rate)與Qbd (charge-to-breakdown) 方面隨著溫度不同而有著明顯的不對稱變化。zh_TW
dc.description.abstractThe characteristics of gate oxides and polysilicon oxides with in-situ HF vapor cleaning and nitrogen incorporation have been investigated. A native-oxide-free silicon surface is prepared. Difference contact hole treatment ways were used to compare the difference between conventional wet HF and new in-situ vapor HF process. The cluster in-situ HF vapor instead treatment and in-situ doping poly-Si deposit process was used to prevent the samples to expose the surface to the air. The contact resistance of poly-plug contact source/drain structure is reduced. Besides, a high performance and reliable deep-submicron n-MOSFETs with ultra-thin gate oxide has been demonstrated. An additional in-situ HF vapor cleaning and transferring of wafers in the closed ambient can reduce the re-growth of native oxide and improve the surface roughness. Our results also indicate that the performance, including the leakage current of ultra-thin gate oxide, the drain current (Id), and transconductance (Gm) of n-MOSFETs with 4 nm thin gate oxides are all significantly improved. The interface states, the stress-induced leakage current and the hot carrier immunity of n-MOSFETs are significantly improved for the native-oxide-free gate oxide. We demonstrate a high performance and reliable deep-submicron n-MOSFETs with ultra-thin gate oxide prepared by combining with nitrogen gate electrode implant and native-oxide-free in-situ HF vapor pre-oxidation cleaning. The performance and reliability, including the leakage current of ultra-thin gate oxide, charge-to-breakdown (Qbd), the drain current (Id), transconductance (Gm), charge pumping current (Icp), stress induce leakage current (SILC), and hot carrier reliability of n-MOSFETs with 4 nm thin gate oxides are all significantly improved. The improved reliability and performance are attributed to the native-oxide-free process, the smooth interface, the incorporation of nitrogen and less As incorporation in the gate oxide resulting from HF vapor clean and nitrogen implantation. The high quality polysilicon oxide grown combining N2O nitridation and CMP (Chemical Mechanical Polishing) process has been proposed. The surface roughness and surface morphology of polyoxide/polysilicon interface are characterized by using AFM and TEM analyses. SIMS analysis is performed to investigate depth profiles of phosphorous and nitrogen. Experimental results indicate that polyoxide grown on the CMP sample exhibits a lower leakage current, higher dielectric breakdown field, higher electron barrier height, less electron trapping rate, higher charge-to-breakdown (Qbd), and lower density of trapping charge than those of Non-CMP samples. In addition, the CMP process enhances nitrogen incorporation at the interface by the N2O nitridation, ultimately improving the polyoxide quality. Moreover, the CMP process smoothens the surface of polysilicon and this planar surface reduces the out-diffusion of the phosphorous during thermal oxidation. Furthermore, the integrity of TEOS polyoxide with CMP process and a high temperature RTA N2/N2O annealing has been studied. Polyoxides deposited by LPCVD TEOS with combination of CMP and RTA show superior performance in term of improved J-E curve, higher charge to breakdown and lower electron trapping rate. The characteristics of TEOS polyoxide annealed in N2O at different temperatures were also discussed. In addition, the surface roughness and surface morphology of polyoxide/poly-Si interface are characterized by using AFM and TEM analyses. SIMS analysis is performed to investigate depth profiles of nitrogen. Besides, with the different annealing temperature, the bilayer (TEOS deposited and thermally grown by RTA) polyoxide film introduces the asymmetry on the electrical leakage current, trapping characterization and Qbd for the different polarity (+Vg and –Vg) injection. Chapter 2 Native-Oxide-Free Surface Prepared by In-Situ HF Vapor Cleaning Chapter 3 Characteristics of Deep-Submicron n-MOSFETs by Nitrogen Implantation and In-situ HF Vapor Clean Chapter 4 Characteristics of Thermal Polysilicon Oxides by N2O Nitridation and CMP Processes Chapter 5 Characteristics of TEOS Polysilicon Oxides by CMP Process and High Temperature RTA N2/N2O Annealing Chapter 6 Conclusions and Recommendations for Future Worksen_US
dc.language.isoen_USen_US
dc.subject氫氟酸氣態清洗zh_TW
dc.subject氮摻雜zh_TW
dc.subject閘極氧化層zh_TW
dc.subject複晶矽氧化層zh_TW
dc.subjectHF Vapor Cleaningen_US
dc.subjectNitrogen Incorporationen_US
dc.subjectGate Oxidesen_US
dc.subjectPolysilicon Oxidesen_US
dc.title氫氟酸氣態清洗及氮摻雜於閘極氧化層與複晶矽氧化層之應用zh_TW
dc.titleThe Applications of In-Situ HF Vapor Cleaning and Nitrogen Incorporation for Gate Oxides and Polysilicon Oxidesen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
Appears in Collections:Thesis