利用超高真空化學分子磊晶系統成長單晶矽鍺源/汲極的正型金氧半電晶體之相關製程研究

Abstract

在本論文中，我們以超高真空化學分子數磊晶系統成長單晶矽與矽鍺磊晶層，並以室溫及高溫來濺鍍鈷金屬與單晶矽鍺反應，在反應的過程中，以鍺比例居多的矽鍺析出物及鈷與矽鍺的三元反應，可由穿透式電子顯微鏡與X光繞射發現，並可分析及比較不同鍺含量、濺鍍方式及摻雜濃度下，鍺在析出物及三元反應中比例的變化；此外，由高能X光繞射的結果可以得知，高溫濺鍍或高濃度硼原子摻雜均可以減緩晶格鬆脫的程度。並且，高濃度的硼摻雜會造成更明顯的鍺原子聚集，我們試圖以一簡單的原理解釋這些現象。並且針對高溫濺鍍中高比例的鍺原子及無依循基板方向的特質等，提出在金屬矽化反應中鈷-矽-鍺混和態區的理論。 利用超高真空化學分子束選擇性磊晶成長的技術，研製硼摻雜矽鍺淺接面正負接面，以期能應用於矽鍺磊晶源/汲極金氧半電晶體之元件應用上，藉由漏電流的分析，擷取二極體接面最佳化的條件，並研究不同鍺含量之磊晶層其介面晶格差排及氧化層端缺陷的差異，再者針對不同的雜質活化退火的條件，一一比較其淺接面之接面深度。 利用超高真空化學分子磊晶系統選擇性成長單晶矽鍺磊晶層的技術，我們成功地製作了以矽鍺為源/汲極的正型金氧半電晶體，在閘極兩旁的隔離層之製程後，在源/汲極端同時選擇性地磊晶隆起之矽及矽鍺磊晶層，以期能同時降低金屬接面電阻及平面電阻，經由電性量測，我們可以證明較高比例的矽鍺可以最有效的改善元件的基本特性。此外，基於源/汲極的隆起構造，元件的短通道效應及汲極高電壓造成的能帶減短效應均可獲得改善。此新型的結構並可以有效的減少離子佈植對源/汲極與矽基板接面的傷害並降低元件之漏電流。最後，藉由低溫量測（-50oC），我們證明矽鍺的新型結構在低溫的改善程度更大。基於這些特質及優點，再加上不複雜的新製程整合步驟，不需另加光罩或黃光程序，使得此新結構在未來的0.1微米金氧半電晶體將深具潛力。

As the transistors continue to scale down, the characteristics of Co/Si1-xGex junction have received lots of attention because of its potential applications to heterojunction bipolar transistors. We have fabricated Co/Si1-xGex junction using room-temperature and high-temperature (i.e., at 450oC) sputtered Co on top of strained Si0.86Ge0.14 and Si0.91Ge0.09 layers prepared by ultra high vacuum chemical molecular epitaxy (UHVCME). The relative composition of Ge in Ge-rich Si1-zGez precipitate and the solid solution of ternary phase silicide of Co-Si-Ge system were compared between room-temperature and high-temperature sputtered samples. We found that the high-temperature-sputtered and boron-doped samples are more effective in inhibiting lattice relaxation, which would be beneficial for manufacturing metal silicide/Si1-xGex structure devices. Mechanisms were proposed to explain the large difference between the room-temperature and high-temperature sputtered samples. It is believed that the mixed Co-Si-Ge solution on high-temperature-sputtered samples is responsible for the different silicidation behaviors. Strained boron-doped Si1-xGex layers with different Ge mole fractions were selectively deposited by ultra high vacuum chemical molecular epitaxy (UHVCME) to form shallow p+-n junction suitable for raised source/drain metal oxide semiconductor field effect transistor (MOSFET) applications. Detailed electrical characterizations were performed. Our results show that the reverse leakage current could be optimized by a rapid thermal annealing (RTA) at 950oC for 20 seconds, and a near perfect forward ideality factor (i.e. < 1.01) is obtained for the p+-n Si1-xGex/Si junction. By analyzing the periphery and area leakage current components of p+-n Si1-xGex/Si junctions with various perimeter lengths and areas, the degree of misfit dislocations and undercut effect were studied. The specific contact resistance was found to decrease as Ge mole fraction increases. Junction depth measurements also show that the junction depth decreases monotonically with increasing Ge mole fraction. The reduced B diffusion constant is attributed to the increasing Ge gradient in the transition region. P-channel MOS transistors with raised Si1-xGex and Si source/drain (S/D) structure selectively grown by ultra high vacuum chemical vapor deposition (UHVCVD) were fabricated for the first time. The impacts of Si1-xGex and Si epitaxial S/D layer on S/D series resistance and drain current of p-channel transistors were studied. Our result show that the new device with Si1-xGex raised S/D layer depicts only half the value of the specific contact resistivity and S/D series resistance (RSD), compared to the device with Si raised S/D layer. The improvement is even more dramatic, when comparing to the conventional device without any raised S/D layer, i.e., RSD of the new device with Si1-xGex raised S/D is only about one fourth the value of the conventional device. Moreover, the device with raised SiGe S/D structure produces a 29% improvement in transconductance (gm) at an effective channel length of 0.16 mm. In addition, Well-behaved short channel characteristics with reduced drain-induced barrier lowering (DIBL) and off-state leakage current are demonstrated on devices with 100nm Si1-xGex RSD, due to the resultant shallow junction and less implantation damage. Moreover, temperature measurements reveal that Si1-xGex RSD devices show more dramatic improvement in device performance at low temperature (-50oC) operation, which can be ascribed to the higher temperature sensitivity of the Si1-xGex sheet resistance. These performance improvements, together with several inherent advantages such as self-aligned selective epitaxial growth (SEG) nature and the resultant T-shaped gate structure, make the new device with raised Si1-xGex S/D structure very attractive for future sub-0.1mm p-channel MOS transistors.