低臨界電壓雙金屬閘極金氧半電晶體製作技術之研發

Abstract

隨著互補式金氧半電晶體(C-MOSFETs)的持續微縮，複晶矽閘極在45奈米以下技術將遭遇到許多本質上的限制，包括高電阻率、硼穿隧和複晶空乏。除此之外，高介電常數介電質也將導入製程以取代傳統二氧化矽或氮氧化矽介電質。然而，有研究指出複晶矽閘極跟高介電常數介電質間會有費米能階栓(Fermi-level pinning)效應。因此，金屬閘極顯然是解決以上問題的良好選擇。使用金屬閘極必須符合適當功函數、熱穩定、製程兼容性和更佳的元件效能等需求。在本論文研究中，包含全金屬矽化(FUSI)閘極和低溫處理純金屬閘極這二種類型雙金屬閘極製程技術的研究。 首先，我們先微縮等效氧化層厚度(EOT)從1.6奈米到1.2奈米，並使用矽化鉿閘極這方面的研究。我們從臨界電壓(Vt)和電子移動率來觀察發現等效氧化層厚度1.2奈米之氮氧化鑭鉿N型金氧半電晶體，在使用低功率數高溫穩定的矽化鉿閘極有良好的效能。自我對準以及閘極優先的矽化鉿╱氮氧化鑭鉿N型金氧化電晶體擁有簡單的高溫全金屬矽化處理以及兼容於現今極大型積體電路整合(VLSI)生產線等優點。 在接下來的研究，我們使用與之前類似的矽化銥全金屬矽化製程。我們可以從極低的漏電、良好的電洞移動率、1000度C高溫穩定性中看出良好的矽化銥╱氮氧化鑭鉿P型金氧化電晶體元件整合特性。然而，在等效氧化層厚度1.2奈米下卻觀察到不佳的平帶電壓和高臨界電壓。因此，我們目標是發展出一種新的製程技術來解決這個問題。 為了研究平帶電壓下滑的現象，我們首先比較使用相同矽化銥閘極在不同等效氧化層厚度下的平帶電壓。最後我們研發出一個新的高功率數銥╱氧化鑭鉿P型金氧半電晶體，使用低溫處理淺接面製程。自我對準銥╱氧化鑭鉿P型金氧半電晶體的優點為適當的5.3電子伏特之等效金屬功率數、+0.05伏特之低臨界電壓、在電場為-0.3 MV/cm下90 cm2/V-s之高電洞移動率以及20 mV之微小偏壓溫度不穩定性(在85度C，10 MV/cm以及一小時的條件下)。本實驗結果擁有1.2奈米等效氧化層厚度、和簡單的自我對準製類似以及閘極優先之極大型積體電路製程，比之前發表的金屬閘極高介電常數介電質P型金氧半電晶體結果不相上下或是較佳。 最後我們也試著同時降低N型金氧半電晶體的製程溫度，使用鉿╱氧化鑭鉿固態擴散製程。我們研究兩種不同的固態擴散製程。結果發現使用低功函數鉿閘極的氧化鑭鉿N型金氧半電晶體在1.2奈米等效氧化厚度下，在臨界電壓以及移動率的觀點都有良好的特性。自我對準閘極優先的鉿╱氧化鑭鉿N型金氧化電晶體擁有的優點包含低於900度C之低製程溫度、良好的元件特性以應用在極大型積體電路製程上。 總結，金屬矽化物的全金屬矽化物製程擁有適當的金屬功率數、高溫穩定等優點。然而當氧化層厚度持續的微縮，1000度C的摻雜活化處理變得越來越關鍵。在我們的研究中，使用低溫製程技術可以解決平帶電壓下滑以及不需要的高臨界電壓。因此在我們末來的研究中，同時對N型與P型金氧半電晶體更進一步減低製程溫度技術是必要的。

With the continuous scaling trend of complementary metal-oxide-semiconductor field effect transistors (C-MOSFETs) technology, poly-silicon gates encounter several inherent drawbacks beyond the 45 nm technology node including high resistivity, boron penetration and poly-depletion. In addition, high-□ gate dielectrics have also been introduced to replace the conventional silicon dioxide or silicon oxynitride. However, poly-silicon gates have reported to suffer from Fermi-level pinning effect at the poly-silicon/high-k interface. Therefore, metal gate is obviously a good choice to solve the above problems. The introduction of metal gates should meet the requirement of proper work function, thermal stability, process compatibility and better device performance. In this dissertation, two novel dual metal gate process technologies including fully silicided (FUSI) gates and low-temperaure-processed pure metal gate were investigated. At first, scaling the effective oxide thickness (EOT) from 1.6 nm to 1.2 nm using HfSix gates was studied. We have found good performance in terms of threshold voltage (Vt) and mobility for Hf0.7La0.3ON n-MOSFETs at 1.2 nm EOT using a low work-function and high-temperature-stable HfSix gate. The self-aligned and gate-first HfSix/HfLaON n-MOSFETs have the advantages of simple high temperature FUSI processing and compatibility with current very large scale integration (VLSI) lines. In the following study, similar FUSI process using IrSix gates was also investigated. Good device integrity of Ir3Si/HfLaON p-MOSFETs is shown by the very low leakage current, good hole mobility and 1000oC thermal stability. However, poor flat band voltage (Vfb) and high Vt is observed at 1.2 nm EOT. As a result, we aimed to develop a new process technology to solve this problem. In order to study the origin of Vfb roll-off phenomenon, we compared the Vfb of Ir3Si gates under different EOT. Finally, we develop a new process technology of high work-function Ir/HfLaO p-MOSFETs using low-temperature-processed shallow junction. The merits of self-aligned Ir/HfLaO p-MOSFETs are the proper □m-eff of 5.3 eV, low Vt of +0.05 V, high hole mobility of 90 cm2/V-s at -0.3 MV/cm and small BTI of 20 mV (85oC, 10 MV/cm & 1 hr). These results are comparable with or better than the previous reported data for metal-gate/high-k□p-MOSFETs, with small 1.2 nm EOT, similar simple self-aligned and gate-first process for VLSI IC fabrication. Finally, we also tried to decrease the process temperature of n-MOSFET by Hf/HfLaO using solid phase diffusion (SPD). Two different SPD shallow junctions were studied. We have found good performance in terms of Vt and mobility for HfLaO n-MOSFETs at 1.2 nm EOT using a low work-function Hf gate. The self-aligned and gate-first Hf/HfLaO n-MOSFETs have the advantages of ≤900oC low processing temperature and good device performance for VLSI fabrication. In conclusion, metal silicide FUSI processes have the advantage of proper □m-eff, high temperature stable. However, as the continuous scaling of oxide thickness, the thermal budge of 1000oC dopant activation process has become more critical. In our study, the Vfb roll-off and unwanted high Vt can be solved by low temperature process technology. As a result, it is necessary to further decrease the process temperature for both n- and p-MOSFETs in our future study.