标题: | 复晶矽薄膜电晶体之制程与可靠度之研究 Study on the Process and Reliability of Poly-Si Thin-Film Transistors |
作者: | 桑任逸 Jen-Yi Sang 雷添福 Tan-Fu Lei 电子研究所 |
关键字: | 复晶矽薄膜电晶体;可靠度;掺氟矽玻璃;多重通道;双极性接面电晶体效应;poly-Si TFT;reliability;FSG;multi-channel;parasitic BJT |
公开日期: | 2004 |
摘要: | 在本论文中,首先,我们提出在掺氟矽玻璃(FSG)上制造的复晶矽薄膜电晶体。实验结果显示元件的电特性和均匀度可藉由掺杂适量的氟原子达到明显的改善。与传统复晶矽薄膜电晶体相较之下,制造在掺氟矽玻璃上的复晶矽薄膜电晶体具有较高的导通电流及场效迁移率,并使得漏电流降低。这是因为氟原子能修补复晶矽与绝缘层介面处及位于通道中复晶矽晶格边界的缺陷。再者,由于氟与矽原子可形成较强的键结,经过热载子应力(hot carrier stress)测试后,发现掺入氟原子的复晶矽薄膜电晶体具有较好的可靠度。 接着,我们进行有关多重通道(multi-channel)复晶矽薄膜电晶体的研究。藉由增加通道的数目来提高闸极的控制能力,可以改善元件的电特性;包括提高导通电流,降低临界电压(threshold voltage)及次临限摆幅(subthreshold swing)。然而,元件的可靠度却会因此而变差。我们推测是由于在多重通道的结构中,靠近汲极端的电场强度会增加,而导致更严重的碰撞游离(impact ionization)所造成。 最后,我们探讨有关复晶矽薄膜电晶体生命周期(lifetime)的问题。发现到最糟的热载子应力测试条件是在闸极电压大约等于临界电压的情形下,而非传统上闸极电压等于二分之一汲极电压。此外,亦发现到在高的汲极电压(drain voltage)应力测试条件下,导通电流随时间的劣化具有相同的斜率,生命周期的分布亦呈线性关系,因为在此情形下元件的伤害主要是由碰撞游离(impact ionization)所造成。然而,在低的汲极电压(drain voltage)测试条件下会有不同的现象发生。这是因为此时必须考虑寄生双极性接面电晶体效应(parasitic bipolar junction transistor action)。 In this thesis, first, a process-compatible scheme for fabricating poly-Si TFTs on an FSG buffer layer was proposed and demonstrated. Experimental results reveal that remarkably improved device performance and uniformity can be achieved with appropriate fluorine concentration. The poly-Si TFT fabricated on FSG layers has a higher on-current, a lower leakage current, and a higher field-effect mobility compared with the conventional poly-Si TFT. The fluorine atoms can passivate the Si/SiO2 interface states and grain boundary trap states in the poly-Si. Furthermore, the incorporation of fluorine also increases the reliability of poly-Si TFTs against hot carrier stressing, which is attributed to due to the formation of the rather strong Si-F bonds. Then, Multi-channel poly-Si TFTs were studied. The device’s electrical characteristic such as on-current, threshold voltage, and subthreshold swing were improved with increasing the channel stripes due to the enhancement of gate control capability. However, the device’s reliability was deteriorated. We concluded that electric field strength near the drain side was enlarged in multi-channel structure, causing severer impact ionization. Finally, we studied the lifetime issue of poly-Si TFTs. It was found that the worst-case of stress conditions is under VG□Vth, not VG=1/2 VD. Moreover, it is revealed that under high VD of stress conditions, the Ion degradation has the same slope with stress time and the lifetime distribution has a linear relationship due to impact ionization dominating. However, under low VD, it shows a different phenomenon. We concluded that the parasitic BJT should be considered in these stress conditions. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT009211535 http://hdl.handle.net/11536/66057 |
显示于类别: | Thesis |
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