不同界面層與環狀植入對高介電氧化層CMOS元件可靠性影響之研究

Abstract

當閘極氧化層微縮到約10 Å 時，閘極介電質的穿隧漏電流也隨之呈指數增加。有多種不同的方法被運用來改善元件的性能與可靠度，其中一種選擇就是利用高介電係數閘極氧化層結構來提昇元件性能的目的。而不僅僅是高介電係數閘極氧化層結構被應用在新世代的CMOS元件，為了抑制元件的短通道效應，使用環狀離子植入製程也是不可或缺的。至於以鉿為基底的高介電係數閘極氧化層結構對於環狀離子植入時所造成氧化層邊緣的影響，我們利用一種單一漏電量測技術來量化它。在以鉿為基底的高介電係數閘極氧化層結構，在環狀離子植入製程時會遭受到大原子質量的離子轟擊，如果此時沒有搭配適合的界面氧化層，在氧化層邊緣會受到傷害使得元件嚴重的劣化。 在本篇論文中，主要是在探討不同界面層(Interfacial Layer) 搭配不同環狀離子所產生的效應並比較其優劣。一開始，我們針對不同製程的界面氧化層做單一漏電流的分析，接下來再檢視每一種界面氧化層遇到不同的環狀離子植入製程時所造成的影響。在這裡我們提出的說法是，高介電係數閘極氧化層結構不僅會因環狀離子植入製程的不同而造成不同的退化程度，還會因界面層的不同使得元件降低或增加離子撞擊的傷害。 在本文的後半部，我們也做了一些元件可靠性的測試。由於高溫正偏壓不穩定性的測試對於環狀離子植入製程所成的邊緣傷害並不明顯，所以，我們利用閘極引發汲極漏電與閘極二極體的量測技術去觀察元件的熱載子效應。我們由結果可以發現，臨界電壓的不穩性或轉導退化這兩種指標，在熱載子加壓後，即使是遭受到質量大的離子轟擊，高介電係數氧化層結構會比傳統氧化層結構來的好。這些結果對於使用高介電係數氧化層的CMOS 元件設計，是一重要的參考指標。

With the scaling of gate oxide thickness into 1 nm regime, the gate leakage current will increase exponentially with reducing thickness. Several different methods can be employed to improve device performance and reliability. Among them, high K gate stack CMOS device is a good choice. Not only high K gate stack is needed, but also halo implant process for improving SCE ( short channel effect ) is inevitable. The impact of halo implant specifically on the edge of Hf based high K gate stacks are evaluated by a unique leakage measurement. Halo implants with large AMU ( Atomic Mass Unit ) through ALD ( Atomic Layer Deposition ) Hf based high K dielectric without appropriate IL ( interfacial layer ) may cause unavoidable damage at the gate edge region, which further causes serious degradation of the devices.

In this thesis, extensive study and comparison have been carried out for various IL process with different halo implant species. First, a unique leakage measurement is made for different interfacial layer processes. They include nitrogen free, nitrogen incorporation by plasma and thermal, for the interfacial layers respectively. Next, we examine the influence of different halo implant species on each IL. It was found that halo implant impact on device characteristics, as a result of high K gate dielectric degradation, is strongly dependent on the halo implant species and governed by the IL used.

Reliability test of these devices was then carried out in the latter half of this work. Because the effect of different halo implant on IL is not obvious during the Positive Bias Temperature Instability(PBTI) reliability testing, Gate-Induced Drain Leakage (GIDL) current and Gated Diode measurement are employed to observe the hot carrier stress effect. After the hot carrier stress, it was found that from the observation of Vt instability and Gm degradation results, optimized high K gate stack with even higher bombardment from the heaviest halo implant species exhibits better performance by comparing to the control oxide. These results provide an important guideline for the design of CMOS devices with high K gate dielectric.