四極射頻金氧半電晶體於雙埠量測下的去寄生效應方法與參數萃取之研究

Abstract

無線通訊市場的蓬勃發展帶動了電子產品需求量的大幅上升。在激烈的競爭之下，具備低成本、高整合性、低功率的CMOS元件提供了射頻電路設計者一個很好的選擇。過去，晶圓廠所提供給客戶的元件樣本佈局(sample layout)中，Source和Body是相連接在一起的，其所搭配的模型卡(model card)也是據此而作出。然而，電路設計者實際使用元件進行設計時，並不一定會將S和B連在一起。因此，現在晶圓廠傾向於直接提供給客戶4-Terminal(4T)的樣本佈局，其所搭配的model card也是針對此情況而製作。以更符合實際上電路設計者使用元件的方式。

本論文使用4T的NMOS元件而仍置於2-port的pad之上進行RF量測並且進行參數粹取的工作。本研究對適合於Two-port量測的de-embedding方法以及參數萃取的方式作了一系列詳盡的探討，並提出了一系列適用於4T NMOS置於2-port的de-embedding以及參數萃取之方法。

此外，本論文利用軟體(Calibre-xRC)計算元件內部金屬彼此偶合的電容，並且分析元件佈局的不同對內部金屬電容的變化，探討佈局最佳化的策略。

The fast development of wireless communication market increases the demand of electronic product. Under such a keen competition, CMOS transistor, which has the characteristics of low cost, high integration and low power, provides radio-frequency (RF) circuit designers an excellent choice. In the past, the Source and Body terminals of the MOS sample layout which foundries provide to customers are connected together. However it is not suitable for users. Therefore, foundries tend to provide 4-Terminal (4T) MOS sample layout to customers directly now.

In this thesis, 0.13□m process, 4T NMOS device is used for extraction but still put in 2-port pad to measure. This thesis includes a series of study and brings up a series of de-embedding and parameter extraction methods which are suitable for 4T NMOS under 2-port measurement.

This thesis utilizes software “Calibre-xRC” to calculate the interconnect capacitances coupling between device interconnect metals, and analyzes the capacitance variation to study the strategy of layout optimization.