完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 張伊鋒 | en_US |
dc.contributor.author | Yi-Feng Chang | en_US |
dc.contributor.author | 黃調元 | en_US |
dc.contributor.author | 林鴻志 | en_US |
dc.contributor.author | Tiao-Yuan Huang | en_US |
dc.contributor.author | Horng-Chih Lin | en_US |
dc.date.accessioned | 2014-12-12T02:24:06Z | - |
dc.date.available | 2014-12-12T02:24:06Z | - |
dc.date.issued | 2004 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT009211551 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/66224 | - |
dc.description.abstract | 我們探討具有複晶矽鍺閘極、與電漿增強式化學氣相沉積氮化矽覆蓋層之P型金氧半場效電晶體(PMOSFETs)特性。其中,使用複晶矽鍺閘極,可以有效降低閘極空乏與硼穿透效應;而以電漿增強式化學氣相沉積之氮化矽層,可以提供通道區域內的壓縮應力。由於通道內的壓縮應力增強,P型金氧半場效電晶體之驅動電流隨著氮化矽層厚度增加而增大。同時,我們也探討,具壓縮應變通道的金氧半場效電晶體,其負偏壓溫度不穩定特性(NBTI)。雖然氮化矽覆蓋層可以增大P型金氧半場效電晶體的驅動電流,但負偏壓溫度不穩定效應卻較未覆蓋氮化矽之電晶體更形嚴重。特別是在高溫條件下,氮化矽層造成的區域應力導致較多的介面狀態產生,這可能是由於通道內的應變能量造成大量矽氫鍵結斷裂。而覆蓋氮化矽之P型金氧半場效電晶體,在高溫長時間的應力施加下,由於大部分的矽氫鍵結被打斷,臨界電壓與介面狀態開始呈現飽和現象。電性回復效應可以有效降低介面狀態的產生,因此動態負偏壓溫度不穩定性與交流應力也被用來模擬電路中元件的操作特性。我們觀察到,交流應力頻率強烈影響具有氮化矽覆蓋層元件之臨界電壓改變、與介面狀態產生。 | zh_TW |
dc.description.abstract | A PMOSFET structure featuring poly-SiGe gate and plasma-enhanced CVD (PECVD) silicon nitride (SiN) capping layer was explored. Poly-SiGe gate is useful to reduce gate depletion and boron penetration, while PE-SiN is used to induce compressive strain locally inside the channel region. PMOSFET’s drive current is enhanced as the thickness of SiN layer increases due to increasing compressive strain in the channel region. Negative bias temperature instability (NBTI) characteristics of PMOSFETs with compressive strain in the channel were also investigated. Although PMOSFET with SiN capping layer show enhanced drive current, its NBTI is worsened, compared to its counterpart without SiN capping layer. A lot of interface states are generated especially in high temperature stress of PMOSFET with SiN layer. This is ascribed to a higher amount of hydrogen incorporated during SiN deposition as well as the high strain energy stored in the channel. For PMOSFET with SiN layer, under sufficient long stress time at high temperature, saturation of the threshold voltage and interface states is found, indicating that most Si-H bonds are broken. Dynamic NBTI and AC stress characteristics were used to simulate the switching operation of PMOSFETs in circuits. It is observed that the electrical passivation effect could effectively reduce the generation of interface states. Both threshold voltage shift and interface-state generation are strongly dependent on the frequency of dynamic stress for devices with SiN capping layer. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 矽鍺 | zh_TW |
dc.subject | 形變通道 | zh_TW |
dc.subject | 金氧半場效電晶體 | zh_TW |
dc.subject | SiGe | en_US |
dc.subject | strained channel | en_US |
dc.subject | PMOSFET | en_US |
dc.title | 具有複晶矽鍺閘極與局部形變通道之P型金氧半場效電晶體元件製作與分析 | zh_TW |
dc.title | Fabrication and Characterization of PMOSFETs with Poly-SiGe gate and Locally Strained Channel | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
顯示於類別: | 畢業論文 |