奈米碳管電晶體之遲滯效應研究

Abstract

自1998年起奈米碳管電晶體(CNTFET)首次被製作出來, 其電性如載子遷移率、載子傳輸、截止頻率..等，已被許多研究單位廣泛地研究。其中碳管電晶體之遲滯效應也為研究之重點，因為此效應將會影響元件之穩定度。另一方面而言，遲滯效應顯示碳管電晶體可應用在感應器或記憶體方面之可能性。自2002至今，研究學者對其遲滯效應之產生機制有兩種看法:一為大氣中水氣吸附至碳管表面所產生之遲滯效應，二為由於閘極偏壓產生之高電場導致碳管中之載子注入介電層所致。 本論文在不同條件下，觀測碳管電晶體之遲滯效應。包括了增加水氣及酒精之極性分子、真空、不同溫度、覆蓋薄膜、照光等環境。也製作了上閘極以及下閘極與源極和汲極電極重疊和不重疊結構之碳管電晶體。經由量測發現，當碳管（通道）暴露於大氣環境中，其遲滯效應會由水分子主導。增加極性分子其遲滯效應會有增強之效果。但是當去除水分子之影響後（如真空環境下），其遲滯效應將由載子注入至介電層機制所致。欲得到穩定之碳管電晶體，碳管（通道）必須隔離極性分子。再者與碳管接觸之介電層必須為低缺陷密度之介電層以及較低的閘極操作電壓。 我們評估利用碳管電晶體遲滯效應作為記憶體元件之可行性。我們發現碳管電晶體記憶體元件其電荷保留時間約數千秒，閘極與源極和汲極電極不重疊結構之碳管電晶體其轉態時間可小於0.4ms。鑑於轉態時間低於快閃記憶體，但電荷保留時間過低。然且其讀寫擦之次數可高於106，欲使用碳管電晶體作為記憶元件，尚有需多瓶頸待克服。

Since carbon nanotube field effect transistor (CNTFET) was demonstrated in 1998, electrical properties of CNTFETs such as mobility, carrier transportation, cut-off frequency, etc., were investigated widely by many researchers. Among these properties, the hysteresis effect of CNTFETs is one of the key points because it affects the device stability. On the other hand, the hysteresis effect reveals the possibility for sensor or memory applications. Since 2002, researchers have two perspectives on the mechanism which causes the hysteresis effect. One is the water molecules adsorption on the surface of carbon nanotube and the other one is the carrier injection into dielectric due to the gate bias induced high electron field. In this work, we study the hysteresis effect of CNTFET under different environments, including adding polar molecules (water and alcohol)、in vacuum ambient、at various temperatures、capping with thin film as well as light illumination. Top gate and bottom gate devices with and without gate to source/drain overlap were fabricated. It is found that water molecules dominate the hysteresis effect as carbon nanotube (channel) is exposed to the ambient. Adding polar molecules will enhance the hysteresis effect. But when we exclude the affect of water molecules, for example in vacuum environment, the hysteresis effect is still observed due to carrier injecting into dielectric. These results suggest that to obtain stable CNTFETs, CNT channel must not be exposed to polar molecules. Furthermore, the dielectrics those contact with CNT must have low defect density and the operation voltage must be not too high. The feasibility for CNTFET as a memory device is also evaluated. It is found that the retention time of CNTFET would be several thousands seconds. The switching time of the gate-source/drain non-overlapped device could be less than 0.4msec. It is clear that the switching speed of CNTFET is higher than that of the FLASH device but the retention time is much shorter. Although the read/write/erase cycle can be much higher than 106, to be a memory device, there are still several bottlenecks need to be overcome.