針對H.264/AVC去方塊濾波器及框內編碼之演算法和架構設計

Abstract

數位視訊科技已在我們的日常生活中扮演重要的角色，編碼效能也隨著技術的演進而提升，H.264/AVC是目前最新的國際視訊編碼標準，相較於MPEG-4、H.263、和MPEG-2，分別可節省39%、49%、和64%的資料量，但由於其具有相當複雜之編碼技術及模式選擇，使得運算複雜度也遠高於先前之編碼標準，因此如何設計高效能的運算模組與在不致犧牲H.264/AVC之編碼效能之前提下，降低其運算複雜度，為目前相當重要之課題。本論文中，我們的貢獻主要有三個部分，分別是針對H.264/AVC系統中：方塊濾波器的架構設計、快速框內預測演算法、以及框內編碼器之架構設計。 去方塊濾波器是H.264/AVC視訊編碼系統中的重要模組，用來減少方塊視覺效應，以增進影像品質。佔有不可忽視的運算量，本論文中，我們提出了兩種不同硬體架構，藉由妥善安排資料處理的順序，在不影響輸出結果的情況下，達到更有效的資料利用率與加速處理的效能，和之前的設計相比，第一種架構有控制邏輯簡單的優點，大量的減少控制電路的邏輯閘數目，並減少50%的內部記憶體，第二種架構則可以減少90%的內部記憶體，並達到更快的運算效率。 框內預測利用空間中資料數值的相關性，用來預測將被編碼的資料數值，是H.264/AVC視訊編碼系統中框內編碼的重要利器，在本論文中，我們針對H.264/AVC框內預測提出一個簡單的三步驟演算法，利用各預測模式的方向關係，省略出現機率較低之模式的運算，而整個過程，只固定需要運算六個模式，而不像全域搜尋演算法需要找九種模式。和全域搜尋法相比，約可節省約33%的框內預測運算量，而只損失約1%左右的位元率。 最後，我們提出H.264/AVC框內編碼器的硬體演算法及其架構，所提出的硬體演算法省去複雜的平面預測模式，減少佔整體面積最大的框內預測模組，且藉由改善的代價函數來增進壓縮的效能。配合高效能的硬體架構和運算流程，可以117.28MHz下，進行即時的HDTV(1280x720) 30fps編碼。 簡而言之，我們對H.264/AVC視訊編解碼系統的貢獻主要有三個部分。我們提出的去方塊濾波器架構可以更有效率的加速去方塊處理；快速框內預測演算法可以有效減少預測所需的運算量；我們所提出的框內編碼架構可以加快框內編碼的速度。

Digital video technology has played an important role in our daily life. With the evolution of video technology coding efficiency has been greatly improved. H.264/AVC is the latest international video coding standard that can save 39%, 49%, and 64% of bit-rates in comparison with MPEG-4, H.263, and MPEG-2, respectively. However, this efficiency comes with the cost of much higher computational complexity than previous standards due to the complex coding approaches and mode decision techniques. Thus, how to design high performance functional units and reduce computational complexity without too much degradation in coding efficiency are very important topics. In this thesis, we have three contributions for the H.264/AVC design, architecture design of the deblocking filter, a fast intra prediction algorithm, and an architecture design of intra coding in H.264/AVC. Deblocking filter is an important component of H.264/AVC to reduce the blocking effect and to improve the video quality. It is both computational and memory extensive. In this thesis, two different architecture of deblocking filter are proposed. The computing flow is reordered for efficient data reusability and high throughput while maintain standard compatibility. In the first version, gate count is greatly reduced by simple control unit, and internal memory is also reduced to 50% of that in the previous design. In the second version, the proposed architecture can reduce 90% of internal memory and achieve higher throughput than others. Intra prediction, which uses the information of spatial correlation to prediction the data to be encoded, is an important tool of intra frame coding. In this thesis, we propose a simple fast three step algorithm. The algorithm uses the directional relationship of prediction modes to skip the modes with less probability. Thus, the proposed algorithm can complete the 4x4 intra prediction by only examining six modes instead of nine modes in the full search algorithm. The simulation result shows that the proposed algorithm can maintain similar PSNR quality to that in the full search algorithm with 33% of computation reduction of intra prediction process and only 1% of bit-rate increase. Finally, a hardware oriented algorithm of intra coding and its architecture are proposed. We save the complex and hardware costly plane mode, which occupies the biggest area in the intra prediction unit in the intra coding and improve the coding efficiency with the enhanced cost function. With well designed high performance functional unit and computing schedule, the proposed architecture can easily support real-time intra coding of HDTV 1280x720@30fps video application when clocked at 117.28MHz. In brief, our contribution to H.264/AVC video coding system is in three parts. The first contribution to the deblocking filter architecture can accelerate the deblocking process. The second contribution to the fast intra coding algorithm can reduce the computational complexity of intra prediction. The final contribution to the intra coding architecture can speed up the computation of intra frame coding.