選擇性接觸置換之無電鍍銅導線製程研究

Abstract

積體電路製作技術之成長，元件線幅持續縮減至深次微米，大幅提昇元件操作速度及積體電路之積集度。伴隨著元件尺寸縮減，後段導線亦必須跟隨微型化且單一層導線已不敷使用，必須建構多層內導線(interconnect)才足以全部連結。與元件微型化不同，導線傳輸速度會隨其尺寸縮減而更遲緩，即所謂之導線RC 延遲，縮短導線長度可以減少RC延遲，但是必須付出更多層導線結構製作，使得製程複雜度提高致使產率下降，必須更換阻值更低之導線及介電常數更低之介電層。在0.25微米元件線幅製程以下時，其導線延遲已超出元件操作速度，所以必須更換低電阻率金屬銅為導線及低介電材料介電層(k=2)，以克服導線時脈訊號傳輸之瓶頸。故低電阻銅導線配合低介電常數介電膜之多層導線結構已被提出應用於0.18微米元件線幅積體電路製作。而當尺寸持續縮小，傳統的 PVD 及 IMP 方式所沉積及濺鍍的銅晶種層(Seed Layer) 已經面臨到鍍附不均勻以及無法順利達到溝渠底部的窘境，除此之外，銅金屬導線以及銅擴散阻障層氮化鉭兩物質在化學機械研磨時，磨除率不同亦會造成金屬導線淺碟化和周圍介電質磨蝕的問題。因此，在此論文中，將提出兩種利用電化學氧化還原置換方式來解決以上所述的種種問題，並針對其所鍍附出來的銅膜性質加以探討研究。 在本研究中，先利用非晶系矽膜與銅離子利用電化學接觸置換法，使銅導線可以選擇性的形成於溝渠中，而因為其選擇性鍍附的優點，可以避開複雜的銅金屬以及阻障層、介電質之間的磨除率的控制問題，並可以克服習知因銅金屬的化學機械研磨所造成的銅導線之碟化現象和介電層的磨蝕問題。 除此之外，另外一種方法亦在本研究中提出，利用電化學的接觸置換反應，將阻障層的鉭或氮化鉭至於接觸置換溶液中，此溶液係用銅離子、氟離子含無水極性有機溶液，將阻障層表面氧化並形成同還原於其表面而形成銅活化晶種層的方法，之後再進行無電鍍銅的製成，選擇性的將溝渠填滿銅金屬，形成銅導線。同樣可以達到解決先前提出的種種問題並達到目前現階段技術的需求與標準。

As interconnect features size shrink down to deep sub-micron region, and the overall chip speed would be limited mainly to the on-chip interconnect RC delay, not to that of device gate RC delay, and copper interconnect have been recognized as the promising mainstream for its application on high performance, and reliability for ultra-large scale integration (ULSI) semiconductor manufacturing. The current main-stream of copper metallization method is carried out by blanket Cu electroplating deposition capable of gap-filling into high-aspect-ratio vias and trenches, and implement of multi-step Cu chemical mechanical polishing (CMP) to remove the overburden Cu and TaN barrier outside of features, known as the Damascene or metal-inlaid process. The multi-step Cu CMP to precisely remove copper and tantalum or titanium nitride barrier outside the trenches without Cu over-polish would be difficult owing to the unequal removal selectivity. On the other hand, regarding the increasing aspect ratio of wires and vias, conventional physical vapor deposition (PVD) Cu seeding for the following Cu electroplating would face the step-coverage limit beyond 0.10 μm tech-node due to the poor sidewall and bottom corners coverage or overhanging on the top corners. Although the chemical vapor deposition (CVD) or electroless Cu seeding could benefit from excellent step coverage, but Cu seed formed by CVD method would suffer from the carbon or nitrogen impurities decomposed from of the metallic-organic precursors and rough surface In our study, we proposed a novel selective Cu metallization process by electrochemical contact displacement, instead of the troublesome Cu seeding and electroplating, and the complicated multi-step CMP process. Implement of the intrinsically selective Cu contact displacement from amorphous Si and the relative simple Si CMP to remove the overburden Si outside of the trenches, the selective Cu metallization can be carried out. The quality of deposited Cu film, like the electrical resistance, crystal grain orientation, adhesion to the underlying Ta barrier layer, would be evaluated by means of sheet resistance, X-ray diffraction, and stud pull testing. In addition, a novel selective galvanic deposition of Cu seed directly on the Ta barrier is also evaluated in this work. It would benefit from not only the good gap-filling capability but also the intrinsic selective deposition on the Ta barrier. In order to selectively forming Cu seed within the trenches, Ta barrier outside of trenches would be removed by CMP. After Cu seed formation, electroless plating using alkaline formaldehyde chemistry could be carried out to selectively depositing Cu into trenches. By means of this approach, both of the step-coverage issues of Cu seeding and complicated multi-step Cu CMP could be overcome.