标题: | 考虑障碍物绕线及缓冲器插入之方法研究 Algorithms for Efficient Buffered Interconnect Tree Construction with Blockages |
作者: | 游宗达 Tsung-Ta Yu 陈宏明 Dr. Hung-Ming Chen 电子研究所 |
关键字: | 效能导向绕线;缓冲器插入;Performance Driven Routing;Buffer Insertion |
公开日期: | 2004 |
摘要: | 近来,由于导线延迟己凌驾于电晶体延迟的缘故,致使许多效能导向的绕线及插入缓冲器的演算法,相继被提出,以降低导线的延迟。在我们的论文当中,我们提出了两种有效率的方法,可以快速建构出效能导向的绕线及插入缓冲器,并考虑避开障碍物的限制。 第一个演算法,我们修改了[8]中使用的降温演算法,以阶层的方式建构绕线,并同时考量插入缓冲器的效应。第二个演算法,我们采用两级最佳化的方式,来达成绕线和插入缓冲器的任务,首先建构出效能导向的绕线之后,再插入缓冲器,以降低导线的延迟效应。 最后,我们所提出的两个方法,与过去所提出的演算法相比,能够得到更好的效能,且所需要的运算时间大幅减少。 In recent years, many algorithms for buffered interconnect tree construction were proposed to minimize interconnect delay due to the interconnect delay becomes more critical than transistor delay. In this thesis, we proposed two efficient algorithms to construct buffered interconnect tree with blockages. Our first algorithm modifies the simulated annealing algorithm [8] to hierarchically construct buffered interconnect tree considering buffer insertion simultaneously. Our second algorithm adopts two-stage optimization techniques to construct buffered interconnect tree. First to construct a performance-driven routing and then insert buffers for it to minimize the interconnect delay. We will show our algorithms could obtain better performance and more efficient than pervious algorithms. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT009211599 http://hdl.handle.net/11536/66723 |
显示于类别: | Thesis |
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