針對晶片匯流排降低電感電容耦合效應之編碼技術

Abstract

在深次微米的製程技術之下，電子元件的體積被持續的縮小，長導線的延遲將會成為決定晶片效能的重要因素。由於電感與電容的耦合效應在長導線上越來越顯著，訊號在一個時脈週期能夠傳輸的距離縮短了許多。為了減少耦合效應，目前為止學者專家已提出了許多種類的匯流排編碼技術以解決這個問題。然而，大部分的編碼技術只考慮了電阻與電容的效應，而電感的效應卻被忽略了。因此，我們在這篇論文中提出了一個有彈性的匯流排編碼技術，它可以明顯降低導線間電感與電容的耦合效應。我們還更進一步將這個編碼技術和曲線近似(curve fitting)結合，以達到在一個時脈週期內增加最大傳輸距離的功能。實驗結果顯示我們的編碼技術可以明顯的降低導線間電感和電容的耦合效應，並且進一步可以增加匯流排的最大傳輸距離。

With the continuous shrinkage of device sizes, the global interconnect delay becomes a dominant factor of chip performance in deep-submicron technology. Furthermore, the signal propagation length in one clock cycle could be greatly reduced due to the strong inductive and capacitive coupling effects on global interconnects. In order to reduce the coupling effects, many bus encoding methods have been proposed. However, most of them consider only resistance and capacitance effects. In this thesis, we propose a flexible bus encoding flow that can reduce the inductive and capacitive coupling delay on on-chip bus. In addition, combining with a curve fitting method, our encoding scheme can be utilized to increase the maximum propagation length in one clock cycle. Simulation results show that our flow can significantly reduce the inductance and capacitance coupling delay and, hence, increase the maximum propagation length of the given bus structure.