硬體/軟體共同設計：以下一代的單一晶片個人數位助理為例

Abstract

半導體製程技術的不斷進步，使得複雜的系統可能整合在單一的晶片上，這些系統晶片 (System-on-Chip, SoC) 包含了特定用途的硬體元件、處理機、記憶體等等。由於一部份的功能由軟體達成，所以在設計硬體的同時，也必須要設計嵌入的軟體，軟硬體的整合使得系統晶片發展困難。 在系統晶片中，系統層級的設計佔了決定整體成敗的關鍵性角色。在這篇論文中，我們將單一晶片個人數位助理的主要元素抽取出來，配合 Cadence® Virtual Component Co-Design 這套系統來完成硬體-軟體的劃分，幫助我們考量硬體/軟體分割與硬體的規格。我們實作了 H.263 編碼解碼器，藉由預估最終系統的執行效能，最後決定將系統以 ARM9 搭配 DSP 的形式實現。

Continued improvement in semiconductor process technology enables designer to put a complex system into a single chip. The so-called System-on-Chip (SoC) consist of application specific hardware components, processors, memory etc. Because of some functionalities will be implemented with software, hardware platform and embedded software should be developed together from starting point. This integration makes design of SoC difficult. Considering System-on-Chip, system-level design plays an important role in the outcome of development. In this thesis, we draw main elements from a single chip personal digital assistant, and use Cadence® Virtual Component Co-Design environment to partition off whole system into hardware and software. With it’s help, we can make design decisions in hardware/software partitioning and hardware specification. We implemented a H.263 software codec. According to the estimation of final system performance and implementation complexity, we decide to implement the system with ARM9 and DSP cores as computing engines.