非晶矽薄膜電晶體在閘極交流訊號下之特性與可靠度之研究

Abstract

於本論文中，我們深入探討不同製程參數之非晶矽薄膜電晶體〈amorphous silicon thin film transistors〉在直流與交流電壓下的不穩定性特性，發現臨界電壓偏移是由電荷攫取〈charge trapping〉與能態生成〈state creation〉這兩種不同的機制所共同造成的。在正向電壓應力下，要分辨此二種不同的不穩定機制是不容易的，這是因為這兩種不穩定性同樣都是造成正向臨界電壓偏移〈threshold voltage shift〉。然而，在負向偏壓應力下，則會出現截然不同的結果。當非晶矽主動層具有較高的缺陷密度與高氮含量氮化矽〈SiNx〉之閘極層時，在長時間負向電壓應力下會出現反轉現象〈turnaround phenomenon〉，也就是臨界電壓飄移會從正向偏移轉換成負向偏移。若主動層之缺陷密度〈density of defect states〉低時，此時只有負向臨界電壓偏移之出現。這種臨界電壓偏移轉換現象主要是由於電荷攫取與缺陷能態生成，這兩種發生在非晶矽薄膜電晶體中的不穩定性源相互作用的結果。當一開始以電荷攫取現象為主時，反轉現象則不會發生。 接下來我們則建立一套可同時提供直流〈DC〉與交流〈AC〉電壓訊號的量測系統，用來分析與探討在閘極交流訊號下影響非晶矽薄膜電晶體的不穩定性因素。因此，在本論文中我們改變訊號的極性〈polarity〉、振幅〈amplitude〉、頻率〈frequency〉與高低訊號時間比〈duty ratio〉來觀察元件在交流訊號操作下之特性。我們發現在較低的閘極交流訊號下，缺陷能態生成是其不穩定性的主要來源，雖然電荷攫取現象也隨著同時發生。這種現象同時也在直流偏壓下被觀察到。除此之外，我們也發現在正向直流偏壓應力下，元件的退化〈degradation〉與所施加訊號的頻率無關。然而在負向交流偏壓下，元件特性的退化卻會隨著訊號頻率變動。這是因為訊號延遲效應〈RC time delay〉所致。此種奇特現象源於N型薄膜電晶體的特性。主要原因是在負閘極電壓下，電洞〈hole〉要通過源極〈source〉與汲極〈drain〉而累積在通道〈channel〉處是相當困難的，因此當訊號頻率增高時，沒有足夠的電洞累積而導致能態生成。另一方面，改變施加交流偏壓的高低訊號時間比也會影響到元件的穩定性，我們可以用等效的總脈波時間來解釋此一現象。如果總和時間愈長，則元件特性改變愈明顯。然而對於較小高低訊號時間比，雖然等效時間相同，但是元件特性變動變小。這是因為電荷與生成能態釋放的結果。接下來我們亦討論元件在雙極性交流訊號下的退化情形，並且發現元件的特性偏移是由閘極絕緣層內不同極性之電荷中和〈charge neutralization〉與非晶矽層內的缺陷再分佈〈defect redistribution〉的結果。 除了外施加應力條件對元件可靠度特性的影響外，元件材料本身亦會影響到元件在長時間交流訊號操作下的不穩定性，例如閘極絕緣化層〈gate insulator〉與主動層〈active layer〉，亦會對其可靠度產生影響。因此，我們也探討了在不同製程參數下之非晶矽薄膜電晶體操作在交流訊號下的可靠度。發現電荷攫取主要發生在具有高含矽量之氮化矽〈Si-rich SiNx〉的閘極絕緣層與低氫流量下所成長之主動非晶矽層之薄膜電晶體，另外一方面，缺陷能態生成主要發生在具有高氮含量之閘極絕緣層與高氫流量下所成長之主動非晶矽層之元件。在次臨界電壓特性〈subthrershold swing behavior〉中比較不同閘極絕緣層與主動層所帶來的影響，發現由於在絕緣層內電荷攫取所產生的屏幕效性〈screening effect〉與主動層內之不同缺陷能態密度產生，其特性會出現不同的結果。電荷攫取嚴重之元件，在施加電壓應力後，其次臨界電壓改變小。而缺陷能態密度大之主動層，則在施加電壓應力後，臨界電壓偏移量大。接著，我們亦對訊號頻率與元件的不穩定性加以探討。從中得知，不管施加在閘極訊號之極性為何，矽含量高之元件的臨界電壓偏移皆會與頻率有關。但是，氮含量高之元件的臨界電壓偏移只在施加負閘極訊號，與頻率有關。 最後，我們探討溫度〈temperature〉與光照射〈light illumination〉對元件可靠度特性之影響，發現當在溫度與光照的催化下，會有較大的臨界電壓與次臨界電壓飄移，其部分原因來自於熱加成與光激發所產生的多餘載子〈excess carriers〉所引發的缺陷能態生成所形成的結果。此一現象除了造成較大臨界電壓飄移外，同時也使臨界電壓飄移的截止頻率〈cut-off frequency〉變高。

In this dissertation, the instability of a-Si:H TFTs with different process conditions stressed at DC and AC bias was completely discussed. It was found that the threshold voltage shift is composed of charge trapping and state creation. At the positive bias stress, it is hard to distinguish the two instability sources due to the same direction of ∆Vth caused by charge trapping and state creation. However, turnaround phenomenon of threshold voltage shift appears during the negative bias stress for a-Si:H TFTs with high-defect-density a-Si:H films and N-rich SiNx gate while TFTs with other conditions of a-Si:H and SiNx films do not. Results reveal that the turnaround phenomenon is greatly influenced by charge traps in SiNx and state creation in the a-Si:H layer. When state creation is dominant at low bias stress, the turnaround phenomenon occurs. In contrast, if charge trapping dominates at low bias stress, the turnaround phenomenon does not occur. We setup a testing system that can support the AC and DC signal to do bias stress and measurement. We used the system to study the factors affecting the characteristics of a-Si:H TFTs under the operation of AC signals. The results show that the state creation dominates at low AC gate bias stress although the charge trapping also occurs in SiNx gates, and such cases have also been found under the DC bias stress. In addition, the degradations of a-Si:H TFTs are found to be independent of the AC frequency for the positive polarity but show frequency dependence for the negative polarity due to the RC effect. It is related to the nature of the n-type a-Si:H TFTs. It is more difficult for holes to pass through source/drain composed of n+ a-Si:H layer than electrons. Therefore, there are not sufficient holes to accumulate in channel during per negative gate pulse as signal frequency goes high. Furthermore, the threshold voltage shift is associated with the duty ratio due to the accumulation of stress time and the time of rest. For a small duty ratio, variation of characteristics of TFTs is small owning to detrap of charges and relax of created states. Moreover, the degradation of the a-Si:H TFTs under the bipolar AC bias stress is also introduced. It is found that the instability mechanisms of devices are composed of different charge compensation in SiNx and redistribution of defect states in the a-Si:H layer. In addition to effect of external force such as the bias signal on instability of a-Si:H TFTs, the internal parameters, such as the quality of the gate insulator and a-Si:H layer are also important factors when a-Si:H TFTs are operated in the AC mode. Therefore, the a-Si:H TFTs with different compositions of SiNx gate insulators and a-Si:H layers were stressed at different AC gate biases to investigate the instability mechanisms. Charge trapping is dominant for the a-Si:H TFTs with Si-rich SiNx and low-hydrogen-dilute a-Si:H layer due to different directions of ΔVth at the positive or the negative bias stress. On the other hand, state creation is the origin of the instability for a-Si:H TFTs with N-rich SiNx and high-hydrogen-dilute a-Si:H layer, which originates from positive ΔVth after positive and negative AC gate bias stresses. The subthreshold swing behavior of a-Si:H TFTs with different compositions of SiNx and a-Si:H layer presents distinct results due to the screening effect of the trapped charges in SiNx films and different defect densities. Moreover, the relationship of AC signal frequency and instability of a-Si:H TFTs are also discussed. Threshold voltage shifts of the Si-rich TFTs depend on the frequency regardless of the polarity of AC gate bias. In contrast, the frequency dependence only occurs in the a-Si:H TFTs with N-rich SiNx at negative AC gate bias stresses. Finally, the temperature and light illumination are also important issues when a-Si:H TFTs is operated at the AC mode. This work investigates the temperature and illumination effects on the a-Si:H TFTs at AC gate bias stress. We find the larger threshold voltage shifts and subthreshold swing changes for the Bias-Temperature-Stress (BTS) and Bias-Illumination-Stress (BIS). Thermally enhanced charge trapping and state creation cause the serious degradation of devices characteristics. Excess carriers from thermal-generation electron-hole pairs or photo-excited electron-hole pairs may significantly influence the instability of a-Si:H TFTs during the AC gate bias stress. The instability mechanisms originate from the carrier-induced defect creation enhanced by thermal generation in the BTS case and also emphasized by photo-excitation for BIS case. Both stress conditions will induce a larger threshold voltage shift and higher cut-off frequency than those for simple bias stresses.