應用空氣為極大型積體電路介電質的新製程開發及製程模擬與整合可行性闡明

Abstract

本篇論文旨在探討如何使空氣介質應用於超大型積體電路上。文中包括了空氣介質的製作方法及其中各類製程參數的考量，與其他製程搭配考量，測試圖案的電性量測，並以理論計算為何空氣可填充於金屬線中及建立一個準三維模型來說明此方法形成空洞的連續步驟。 當積體電路的尺寸越做越小時，元件與元件之間的傳輸延遲已漸主導整體系統的效能。為使傳輸速度加快，導線阻值與導線間介質的介電係數必需降低，空氣為擁有最低介電質的物質，不過如何使空氣介質應用於積體電路之上，實為半導體界一重大挑戰。 空氣本身為氣態存在，不擁有固態實體，相較於以往半導體中其他薄膜皆為堆疊於固體之上，在空氣之上繼續沉積其他薄膜及製程成為最大的困難。本篇論文利用倒置製程晶片的方法使欲形成之薄膜位於金屬線與其空氣間隙的下方，以此規避傳統製程中沉積其他薄膜時需將薄膜堆疊於固體之上的限制，而空氣介質便在薄膜成型後形成。形成薄膜的為可旋轉塗佈的低介電質材料，方法則為利用其可流動的特性流過倒置製程晶片下方的間隙並加以烘烤固化及去除承載晶片上之薄膜以形成薄膜。其中間隙高度、低介電質濃度、烘烤固化溫度及方式、金屬線高度及承載晶片上之薄膜特性為空氣介質形成的主要參數。 應用空氣為線與線間的介電質時，介層洞的形成也是重要的考量點。傳統介層洞使用鎢為填充金屬，以化學氣相沉積法沉積鎢膜時若遇圖案位移時，鎢將會填充於空洞之間形成短路。我們採用類似於雙層大馬士革的結構來解決此問題。先以整層覆蓋鎢金屬於未圖案化的金屬導線上，再圖案出介層洞及金屬導線後，才進行空氣介質的形成。如此一來，空洞之間因對不準以至於沉積鎢膜時形成短路的問題就可獲得解決。 大面積空洞的形成為此技術可能為人質疑之處，為此我們於實作上成功製作大面積的空洞。並於理論上計算出重力效應微乎其微，流體流動實由表面張力所主導。因此流體可流過大面積間隙並形成空洞。 我們使用指叉式圖形來進行電性量測，並以熱應力來測試其可靠性。量測結果於攝氏300度條件下仍可存活。與傳統的電漿輔助化學氣相沉積氧化層介質相比，漏電流較小，寄生電容也較小，可靠性則以一般四層金屬視之。其中漏電流經由比對分析，空氣介質的漏電流路徑為經由氧化層的表面能態所產生。 製作空氣介質時，我們發現仍有許多其他參數的設定會決定空氣介質的形成。經由工程上不斷的錯誤嘗試與驗證，我們建立了一套可說明空氣介質形成的基本模型，此模型可分為三部分，第一部份為流動介質可跨過線與線間隙並形成空氣介質的模型，模型中計算一維表面的表面力的影響，並以此求出一可形成空氣介質所需條件，包括流體速度、倒置製程晶片與承載晶片間隙等。第二部份為在已形成空洞時低介電物質不流入空洞的條件模型，此部份計算表面力與開放空洞或封閉空洞內的壓力，由此模型我們可知形成空洞時介質不流入的主因為空洞內壓。第三部分我們依據前二部分撰寫一簡單的C語言程式來描述準三維空洞形成的連續步驟，希望藉此了解圖案與空洞形成的相關性以使將來空氣介質製程介電物質常數的計算能更精準。

This thesis studies how to use air as dielectric material in ULSI. It includes the process flow of air gap, consideration of related process parameter, consideration about compatibility with existed process, electrical characteristics extracted from test pattern, calculation about why liquid will not flow into air gap and a quasi-three-dimension model to describe the steps of air gap formation. As the feature size of IC technology continues to shrink, the transmission delay between device and device gradually dominates the whole chip performance. To improve the transmission speed, we must reduce parasitic resistance of transmission line and decrease the dielectric constant of material between metal lines. Air has the lowest dielectric constant; however, how to integrate air into IC process is a huge challenge for semiconductor industry. Air exists as a gas type and it does not own solid type. It is very hard to deposit any other solid film onto the air like other solid film deposited onto solid film in semiconductor process. In this thesis, we use wafer faced-downward method to form a thin layer below the metal lines and air gaps to shun the limitation that solid film must be deposited onto solid film in conventional IC process. Then, air gap forms after the thin layer is formed. The material of forming the thin layer is spin-on low dielectric constant material. The method is to trickle the liquid material through the slit between the metal lines and bottom polyimide layer on the holder wafer, bake, cure and remove the bottom polyimide layer to form dry thin oxide layer. In the method, slit height, concentration of low dielectric constant material, bake temperature, bake type, metal line height and the characteristic of polyimide layer on the holder wafer are the main parameters to form air gap. To apply air into IC process, we need to consider via formation method of air gap. In conventional IC process, we use CVD tungsten as plug metal. Lucklessly, in applying this method to air gap process, it will cause short circuit when pattern misalignment happens. Consequently, we use a similar dual damascene structure to solve this problem. First, we deposit tungsten film as via metal on the unpatterned metal and pattern these two films with metal lines layout. Second, we pattern via on the tungsten film and use the layout to form air gap. Thus, the short circuit problem from misalignment between metal lines and via will be solved. The large area air gap formation is an issue of this technique, so we manufacture large size air gap, too. We also calculate that the gravity effect is ignored and the main cause of liquid flow is surface tension. Therefore, this technique can form large area air gap. We use cross-finger structure to measure electrical characteristics and test its thermal reliability. The result shows that even no oxide fortify the metal lines, the metal lines can work well in 300℃. The electrical characteristics compared with conventional PECVD oxide also show lower leakage current and lower parasitic capacitance. By comparing the leakage data with basic conduction mechanisms, we can find that the leakage current of air gap path is surface state of oxide. In constructing air gap technology, we find that many other parameters will affect the formation of air gap. By continuous try and modification, we construct a series of basic models to describe the formation of air gap. These models include three parts. In the first part, we construct a model about why liquid low dielectric constant material can flow through the gap between metal lines to form air gap. In this model, we calculate the one-dimension surface tension effect and get that the liquid velocity, the slit between metal lines and polyimide are the important parameters to form air gap. In the second part, we construct a model about why the static liquid layer will not flow into gap. Calculate the open space and closed space pressure respectively and compare the results with atmosphere pressure; we get the main cause is the inner pressure inside the gap. In the third part, we use C language and the results from part 1 and part 2 to program a quasi-three-dimension model to describe the continuous air gap formation procedures. By programming the whole procedures, we can know the effect of pattern on the air gap formation and get more precision value to calculate parasitic capacitance.