标题: 应用空气为极大型积体电路介电质的新制程开发及制程模拟与整合可行性阐明
Development and Process Simulation of A Novel Technology for Using Air as ULSI Dielectric and Integration Feasibility Illumination
作者: 杨知一
Ji-Yi Yang
张 国 明
Kow-Ming Chang
电子研究所
关键字: 空气介质;超大型积体电路;低介电质物质;空气;Air Dielectric;ULSI;Low Dielectric Material;Air
公开日期: 2000
摘要: 本篇论文旨在探讨如何使空气介质应用于超大型积体电路上。文中包括了空气介质的制作方法及其中各类制程参数的考量,与其他制程搭配考量,测试图案的电性量测,并以理论计算为何空气可填充于金属线中及建立一个准三维模型来说明此方法形成空洞的连续步骤。
当积体电路的尺寸越做越小时,元件与元件之间的传输延迟已渐主导整体系统的效能。为使传输速度加快,导线阻值与导线间介质的介电系数必需降低,空气为拥有最低介电质的物质,不过如何使空气介质应用于积体电路之上,实为半导体界一重大挑战。
空气本身为气态存在,不拥有固态实体,相较于以往半导体中其他薄膜皆为堆叠于固体之上,在空气之上继续沉积其他薄膜及制程成为最大的困难。本篇论文利用倒置制程晶片的方法使欲形成之薄膜位于金属线与其空气间隙的下方,以此规避传统制程中沉积其他薄膜时需将薄膜堆叠于固体之上的限制,而空气介质便在薄膜成型后形成。形成薄膜的为可旋转涂布的低介电质材料,方法则为利用其可流动的特性流过倒置制程晶片下方的间隙并加以烘烤固化及去除承载晶片上之薄膜以形成薄膜。其中间隙高度、低介电质浓度、烘烤固化温度及方式、金属线高度及承载晶片上之薄膜特性为空气介质形成的主要参数。
应用空气为线与线间的介电质时,介层洞的形成也是重要的考量点。传统介层洞使用钨为填充金属,以化学气相沉积法沉积钨膜时若遇图案位移时,钨将会填充于空洞之间形成短路。我们采用类似于双层大马士革的结构来解决此问题。先以整层覆盖钨金属于未图案化的金属导线上,再图案出介层洞及金属导线后,才进行空气介质的形成。如此一来,空洞之间因对不准以至于沉积钨膜时形成短路的问题就可获得解决。
大面积空洞的形成为此技术可能为人质疑之处,为此我们于实作上成功制作大面积的空洞。并于理论上计算出重力效应微乎其微,流体流动实由表面张力所主导。因此流体可流过大面积间隙并形成空洞。
我们使用指叉式图形来进行电性量测,并以热应力来测试其可靠性。量测结果于摄氏300度条件下仍可存活。与传统的电浆辅助化学气相沉积氧化层介质相比,漏电流较小,寄生电容也较小,可靠性则以一般四层金属视之。其中漏电流经由比对分析,空气介质的漏电流路径为经由氧化层的表面能态所产生。
制作空气介质时,我们发现仍有许多其他参数的设定会决定空气介质的形成。经由工程上不断的错误尝试与验证,我们建立了一套可说明空气介质形成的基本模型,此模型可分为三部分,第一部份为流动介质可跨过线与线间隙并形成空气介质的模型,模型中计算一维表面的表面力的影响,并以此求出一可形成空气介质所需条件,包括流体速度、倒置制程晶片与承载晶片间隙等。第二部份为在已形成空洞时低介电物质不流入空洞的条件模型,此部份计算表面力与开放空洞或封闭空洞内的压力,由此模型我们可知形成空洞时介质不流入的主因为空洞内压。第三部分我们依据前二部分撰写一简单的C语言程式来描述准三维空洞形成的连续步骤,希望藉此了解图案与空洞形成的相关性以使将来空气介质制程介电物质常数的计算能更精准。
This thesis studies how to use air as dielectric material in ULSI. It includes the process flow of air gap, consideration of related process parameter, consideration about compatibility with existed process, electrical characteristics extracted from test pattern, calculation about why liquid will not flow into air gap and a quasi-three-dimension model to describe the steps of air gap formation.
As the feature size of IC technology continues to shrink, the transmission delay between device and device gradually dominates the whole chip performance. To improve the transmission speed, we must reduce parasitic resistance of transmission line and decrease the dielectric constant of material between metal lines. Air has the lowest dielectric constant; however, how to integrate air into IC process is a huge challenge for semiconductor industry.
Air exists as a gas type and it does not own solid type. It is very hard to deposit any other solid film onto the air like other solid film deposited onto solid film in semiconductor process. In this thesis, we use wafer faced-downward method to form a thin layer below the metal lines and air gaps to shun the limitation that solid film must be deposited onto solid film in conventional IC process. Then, air gap forms after the thin layer is formed. The material of forming the thin layer is spin-on low dielectric constant material. The method is to trickle the liquid material through the slit between the metal lines and bottom polyimide layer on the holder wafer, bake, cure and remove the bottom polyimide layer to form dry thin oxide layer. In the method, slit height, concentration of low dielectric constant material, bake temperature, bake type, metal line height and the characteristic of polyimide layer on the holder wafer are the main parameters to form air gap.
To apply air into IC process, we need to consider via formation method of air gap. In conventional IC process, we use CVD tungsten as plug metal. Lucklessly, in applying this method to air gap process, it will cause short circuit when pattern misalignment happens. Consequently, we use a similar dual damascene structure to solve this problem. First, we deposit tungsten film as via metal on the unpatterned metal and pattern these two films with metal lines layout. Second, we pattern via on the tungsten film and use the layout to form air gap. Thus, the short circuit problem from misalignment between metal lines and via will be solved.
The large area air gap formation is an issue of this technique, so we manufacture large size air gap, too. We also calculate that the gravity effect is ignored and the main cause of liquid flow is surface tension. Therefore, this technique can form large area air gap.
We use cross-finger structure to measure electrical characteristics and test its thermal reliability. The result shows that even no oxide fortify the metal lines, the metal lines can work well in 300℃. The electrical characteristics compared with conventional PECVD oxide also show lower leakage current and lower parasitic capacitance. By comparing the leakage data with basic conduction mechanisms, we can find that the leakage current of air gap path is surface state of oxide.
In constructing air gap technology, we find that many other parameters will affect the formation of air gap. By continuous try and modification, we construct a series of basic models to describe the formation of air gap. These models include three parts. In the first part, we construct a model about why liquid low dielectric constant material can flow through the gap between metal lines to form air gap. In this model, we calculate the one-dimension surface tension effect and get that the liquid velocity, the slit between metal lines and polyimide are the important parameters to form air gap. In the second part, we construct a model about why the static liquid layer will not flow into gap. Calculate the open space and closed space pressure respectively and compare the results with atmosphere pressure; we get the main cause is the inner pressure inside the gap. In the third part, we use C language and the results from part 1 and part 2 to program a quasi-three-dimension model to describe the continuous air gap formation procedures. By programming the whole procedures, we can know the effect of pattern on the air gap formation and get more precision value to calculate parasitic capacitance.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT890428009
http://hdl.handle.net/11536/67078
显示于类别:Thesis