標題: Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network
作者: Liu, Chih-Hao
Lin, Chien-Ching
Yen, Shau-Wei
Chen, Chih-Lung
Chang, Hsie-Chia
Lee, Chen-Yi
Hsu, Yar-Sun
Jou, Shyh-Jye
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Architecture;IEEE 802.11n;IEEE 802.16e;message passing;network;quasi-cyclic low-density parity check (QC-LDPC);WiMax
公開日期: 1-Sep-2009
摘要: A reconfigurable message-passing network is proposed to facilitate message transportation in decoding multimode quasi-cyclic low-density parity-check (QC-LDPC) codes. By exploiting the shift-routing network (SRN) features, the decoding messages are routed in parallel to fully support those specific 19 and 3 submatrix sizes defined in IEEE 802.16e and IEEE 802.11n applications with less hardware complexity. A 6.22-mm(2) QC-LDPC decoder with SRN is implemented in a 90-nm 1-Poly 9-Metal (1P9M) CMOS process. Postlayout simulation results show that the operation frequency can achieve 300 MHz, which is sufficient to process the 212-Mb/s 2304-bit and 178-Mb/s 1944-bit codeword streams for IEEE 802.16e and IEEE 802.11n systems, respectively.
URI: http://dx.doi.org/10.1109/TCSII.2009.2027967
http://hdl.handle.net/11536/6707
ISSN: 1549-7747
DOI: 10.1109/TCSII.2009.2027967
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume: 56
Issue: 9
起始頁: 734
結束頁: 738
Appears in Collections:Articles


Files in This Item:

  1. 000269777400010.pdf

If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.