八位元互補式金氧半子區間式類比至數位轉換器

Abstract

本論文描述一個3.3V，8位元，50MS/s 的類比至數位轉換器。其輸入電壓範圍為 0V~1.024V。此類比至數位轉換器是以子區間式(subranging)的架構來實現，主要包含了約略比較器(coarse comparator)，精密比較器(fine comparator)，參考電壓產生器(reference voltage generator)，數位錯誤修正電路(digital error correction circuit)，和時脈產生器(clock generator)五種主要的區塊。所需的八位元輸出中，先由31個約略比較器產生較高的五位元，再由15個精密比較器產生剩下的三個位元。然後由精密比較結果透過數位錯誤修正電路修正較高的五位元以得到最後正確的八位元輸出。此類比至數位轉換器以TSMC 1P4M 0.35微米製程技術來實現，並經由HSPICE模擬驗證符合八位元的解析度與每秒五十百萬取樣。所耗用的面積為1.3 1.5 ，且在電源供應為3.3V的情況下，總消耗功率為51.84mW。

The thesis describes a 3.3V, 8-bit, 50MS/s analog-to-digital converter. The input voltage range is 0V~1.024V. The A/D converter is implemented by the subranging architecture, including coarse comparators, fine comparators, reference voltage generator, digital error correction, and clock generator, which are the five major blocks. In the required 8 bits output, the 5-bit MSBs are generated from 31 coarse comparators first, and the other 3 bits are generated from 15 fine comparators. Then, from the fine comparing result, the 5-bit MSBs are corrected by the digital error correction circuit to get the final correct 8-bit output. The A/D converter is implemented by TSMC 1P4M 0.35um process, and is verified to achieve 8-bit resolution and 50MS/s by HSPICE simulation. The area including pads is 1.3 1.5 , and the power consumption is 51.84mW at 3.3V power supply.