應用於IEEE802.11a無線區域網路的正交多工分頻技術的基頻傳收器

Abstract

近年來正交多工分頻技術(OFDM)系統已被採用於高速收發器晶片的基頻處理器之中，以應用於IEEE802.11a這個在5GHz頻帶上的高速無線區域網路標準。由於正交多工分頻系統具有長的信號週期有利於消除多路徑通道中的頻率選擇性衰減，能符合高速及高品質傳輸的要求，故正交多工分頻基頻收發器已採用於最先進的高速無線網路系統基頻端處理器。而正交多工分頻系統中的關鍵模組: 快速傅立葉轉換處理器的設計，主導著整個正交多工分頻系統的傳輸效能。為了增進在高速傳輸、硬低體複雜度上和低能量耗損的能力，管線化快速傅立葉轉換處理器的演算法與架構已被發展和討論多年。此外，在正交多工分頻系統中，為了提高資料在頻道傳輸中的準確率，超倍頻取樣被採用在正交多工分頻收發器的接收端，以助於接收端能取樣到最大的訊號能量而得到最大的訊號雜訊比和最低的資料錯誤率。 本篇論文將介紹一個包含N根管線化快速傅立葉轉換處理器的完整正交多工分頻系統。N根管線化快速傅立葉轉換處理器具有即時處理輸入訊號的能力並且能在速度上達到100Mbits/s以滿足超倍頻取樣技術的最高需求，而在硬體架構上的最佳化將會有效降低它的硬體需求。此外，由於在基頻處理器上的快速傅立葉轉換處理器是定點運算設計，量化誤差將會產生，而快速傅立葉轉換處理器的訊號字元長度的解析度將會因量化誤差而影響整個正交多工分頻系統在資料錯誤率上的效能。如此則必須先藉著高階模擬來評估快速傅立葉轉換處理器在硬體上的最佳訊號字元長度後再行實現，於是建立了結合了正交多工分頻系統和AWGN頻道的模擬環境，用以評估正交多工分頻系統在AWGN頻道上傳輸的效能。在這篇論文中將詳盡地介紹完整的正交多工分頻收發器硬體架構、N根管線化快速傅立葉轉換處理器的硬體架構以及結合正交多工分頻系統和AWGN頻道的模擬結果。

Orthogonal frequency division multiplexing (OFDM) system has been applied for high-speed baseband transceiver for IEEE802.11a standard such the wireless LAN (WLAN) in 5GHz band. Due to that OFDM system is an effective modulation technique for high-rate and high-speed transmission over frequency selective fading channels, OFDM baseband transceiver has been applied for advanced high-speed WLAN. This thesis presents a complete architecture of OFDM baseband transceiver. Both high-level simulation and hardware optimization improve the hardware architecture to get high data rate, high transmission performance, and low hardware cost. The simulation environment with OFDM system and AWGN channel has been established in order to estimate performance of overall WLAN transmission system. Due to quantization error induced by OFDM baseband transceiver such a fixed-point approach, the wordlength of FFT, resolution of both digital-to-analog converter (DAC) and analog-to-digital converter (ADC) will influence the error rate performance of OFDM system. So high-level simulation proceeds with AWGN channel. Radix-64 64-point pipeline FFT processor is proposed for low memory requirement. Hardware optimization improves it to a high efficiency of hardware sharing design. For lower synchronization error, dynamic ADC sampling methodology with a digital frequency synthesizer (DFS) is proposed for timing recovery. The all cell-base DFS can reduce turnaround time and improve synchronization performance of OFDM baseband transceiver. The complete hardware architecture of OFDM baseband transceiver, algorithm of radix-64 64-point pipeline FFT processor, and the simulation of OFDM system with AWGN channel will be introduced and discussed particularly in this thesis.