标题: | 绝缘层上有矽互补式金氧半制程技术 ESD ROBUSTNESS OF CMOS DEVICES IN SOI SALICIDE CMOS TECHNOLOGY |
作者: | 洪根刚 Kei-Kang Hung 柯明道 Ming-Dou Ker 电子研究所 |
关键字: | 静电防护;绝缘层上有矽;二极体;金氧半电晶体;ESD;SOI;diode;MOSFET |
公开日期: | 2000 |
摘要: | 积体电路产品之静电放电(ESD)防护设计,随着半导体制程技术的演进已愈来愈重要,积体电路产品的静电放电耐受规格并未因半导体元件的缩小而下降,因而使得晶片上之静电放电防护设计更加困难。先进的半导体制程技术导致互补式金氧半积体电路(CMOS IC)对ESD的防护能力大幅地下降,因此国内外各大IC厂无不针对此一问题投入研发人力及物力,以解决积体电路产品实际应用上必须面对的问题。 随着高阶积体电路产品对电路性能的需求:Low capacitance;Low leakage current;Good sub-threshold I-V Characteristics;Extra low voltage operation;Low power consumption;High radiation hardness;以及High latch-up immunity的良好特性,使得 SOI (silicon-on-insulator)制程技术已经进展到了商业量产化的阶段。而在SOI制程技术所制作的电晶体元件,具有与基底(substrate)隔绝的特性,此种元件的散热能力较一般CMOS制程技术所制作的电晶体元件来的差,当SOI 元件遭受ESD侵袭时,更易被过高的热能所烧毁。由国外多位ESD专家的实验结果可知,具有相同dimension的元件在SOI制程技术下所具有的ESD保护能力要比在一般基底互补式金氧半制程技术来的低,因此其ESD保护的问题更需要特别注意与适当的设计。 本篇论文研究方向为针对SOI制程之ESD保护课题作深入研究,以开发出更适合的ESD保护元件及电路以应用于SOI制程上面。本篇论文共设计了四种不同结构的金氧半场效电晶体以及三种不同结构之二极体,做不同实验条件下静电保护能力的比较。在金氧半场效电晶体方面除了设计多种不同的layout参数以找出最有效的条件外,更加入了两种静电保护电路:包含由闸极驱动式的静电保护电路以及由基极驱动式的静电保护电路。实验结果显示闸极驱动式的静电保护电路的保护能力大于由基极驱动式的静电保护电路,此种现象反而和由目前的CMOS制程所得到的结论不同。另外在SOI制程的二极体设计上,两种新的二极体结构拿来和由IBM公司所发表的Lubistor二极体做比较,实验结果显示新设计的两种二极体元件在直流的特性上,和在静电保护能力上都要比Lubistor二极体优良,显示新的二极体结构具有商业化以及专利申请的价值。 There are two parts included in this thesis, which are related to the MOSFET devices and diode devices in the silicon-on-insulator (SOI) CMOS technology. In the first part, electrostatic discharge (ESD) robustness of CMOS MOSFETs with four different layout structures of H-gate, T-gate, floating-body, and sided-body, fabricated in a 0.15-µm partially-depleted SOI salicide CMOS process are studied and compared. Both of the positive polarity and the negative polarity ESD robustness of these fabricated MOSFETs are verified by ESD tester, and the second breakdown current (It2) of these MOSFETs are also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of these CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process. The ESD robustness raised by gate-driven technique performs more efficient than by substrate-triggered technique. In the second part, novel gated and non-gated diode structures for ESD protection are disclosed. The I-V characteristics of these new diodes under forward-biased and reverse-biased conditions are measured and compared to that of the lateral unidirectional bipolar type insulated gate transistor (Lubistor) diode. The experimental results show that the proposed new diode structures have an improved ESD robustness. A novel design on the power-rail ESD clamp circuit with the gate-triggered diodes in stacked configuration has shown a higher ESD robustness. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT890428090 http://hdl.handle.net/11536/67166 |
显示于类别: | Thesis |