多孔性低介電常數材料之製程整合研究

Abstract

隨著半導體技術的進步，元件的尺寸不斷的縮小，而入深次微米的領域中。為了增加積體電路的性能，降低導線的線寬和增加金屬導線層的數目，便成為超大型積體電路技術所需採用的方式。然而電子訊號在金屬導線間傳遞所造成的延遲，變成半導體元件速度受限的主要原因。為了降低訊號傳遞的時間延遲，使用低介電常數材料作為導線間的絕緣層，便可降低導線間的電容值，使元件在速度方面的性能提高，並且可以降低功率的消耗(power dissipation)及雜訊干擾(cross-talk noise)。在眾多的低介電常數材料中，多孔性的二氧化矽(porous silica)薄膜，是其中極具發展潛力的一種材料。在本論文中，將對二氧化矽薄膜的物性、熱穩定性及電性進行探討。除此之外，在經過氧電漿的過程中會影響到材料的特性，我們也提供一些方法來改善氧電漿所帶來的問題。最後，我們也做了介電材料與銅的可靠性研究。

As ULSI circuits are scaled down to deep submicrom regime, interconnect delay becomes increasingly dominant over intrinsic gate delay. To reduce the RC delay time, many low dielectric constant materials have been developed. Using low dielectric constant materials as inter-metal dielectric, the ICs will work at high speed, low power dissipation, and low cross-talk noise. Among of various low dielectric materials, porous silica films are promising candidates for advanced interconnect systems. The adjustable dielectric property makes porous silica suitable for different IC technology nodes. In this study, the intrinsic properties such as fundamental physical, electrical, and thermal properties of the porous silica have been investigated. The compatibility of the porous silica with integration processes also has been studied comprehensively. We have proposed dry and wet treatments to improve the dielectric properties of porous silica after photoresist stripping. Material and electrical analyses were used to interpret these improvements. Finally, we have also explored the reliability issue related to copper penetration in porous silica film.