應用於 Serial ATA 6Gbps 之可程式化展頻時脈產生器

Abstract

現代的電路系統操作速度越來越快，其所控制時間的電路也越來越重要。因此，鎖相迴路在所有高速的系統中扮演一個非常重要的角色。例如：頻率合成器、倍頻器、資料回復電路等等。因為這些系統需要一個準確的時脈，一個低抖動的鎖相迴路是我們所設計的一個重點。 且隨著晶片操作速度越來越快，時脈信號所造成的高頻電磁雜訊干擾( Electro-Magnetic Interference, EMI )通常會影響到其他電路的操作。且當操作速度越快時，這種問題就越嚴重。傳統的解決方法是將電磁雜訊干擾加以屏蔽，或是控制時脈信號的上升速度，但是缺點是昂貴的成本與龐大的體積。較先進的解決方法是直接在晶片上降低電磁雜訊干擾，以達到低成本與高彈性空間。改變時脈信號的中心頻率是最常被採用的方法。這種方法被稱為展頻時脈技術(Spread Spectrum Clocking)，因為時脈信號的頻譜被展開成較寬的頻帶。 在本論文中，我們先簡單的介紹了鎖相迴路及展頻時脈產生器的基本觀念。並在第五章提出了如何降低電壓抖動的方法以及可程式化展頻時脈產生器的架構。我們的展頻時脈產生器是以調變多重相位的方法來達到展頻的效果並且符合Serial-ATA 6Gbps的規格。可程式化展頻時脈產生器可依系統的需求，選擇對10個輸出相位或是20個輸出相位作展頻。各有各的優缺點，接下來會詳細的討論並驗證之。 本論文包含了鎖相迴路及展頻時脈產生器的設計、模擬、和製作，並且附上鎖相迴路在0.18毫米互補式金氧半的製程實現後的量測結果，證明我們所提出的設計在實現與應用上是可行，並且符合Serial-ATA 6Gbps的規格。

As chips work at faster operation speed, the timing issue becomes more and more important. So the PLL plays an important role in all high-speed systems, such as: frequency synthesizer, clock multiplier, Clock and Data Recovery (CDR) circuit, and clock de-skew application. Consequently, a low-jitter PLL is important because these systems require a stringent timing specification. Due to the operation speed is becoming faster and faster, many higher order harmonics of the signal are generated. These signals often generate Electric-Magnetic Interference (EMI) that affects the operation of other equipments. When the operation speed is higher, the EMI problem is more severe. The conventional techniques to reduce EMI tend to enclose or reduce the amount of the generated radiation, such as shield cables and coaxial wires, but they are usually costly and bulky. Modern EMI reduction is done on-chip without using heavy shielding materials to the goal of low-cost and flexibility. Altering the center frequency of internal clocks is a widely adopted EMI reduction technique. The technique is called Spread Spectrum Clocking (SSC) because the spectrum of the clock is spread over a broader range. It also offers the best immunity with respect to manufacturing process variation. Serial-ATA (SATA) specification defines an EMI reduction method using SSC. A low-jitter programmable spread-spectrum clock generator using switching phases and the modified ∆Σ modulator is presented in this thesis. The circuits are proposed, simulated, and implemented in a standard 0.18um CMOS technology. Our low jitter PLL is achieved through VCO with low KVCO by using medium-threshold voltage PMOS and passive resistance. The spectrum in the clock generator with modulation on phases can be spread by 10 phases or 20 phases depending on the system’s requirement, such as power saving or low jitter in time domain. Besides, the programmable spread spectrum generator is also fit with the specification of Serial-ATA 6Gbps. Finally, the experiment results show that the architecture achieves spread spectrum function as expectations.