應用於前端錯誤更正機制的16位元數位訊號處理器

Abstract

本論文主旨擬在於設計一個應用於前端錯誤更正機制的16位元特殊應用數位訊號處理器。此處理器的向量指令可以改善記憶體存取的表現和程式的大小，針對錯誤更正機制設計的特殊功能單元和對應的資料運算流程使演算法的實現更為簡單且加速解碼的速度。使用0.18μm 1P6M製程實現晶片，139.4K個邏輯閘，晶片的大小約為7.73mm2，其中包含了18k 位元的記憶體。在解里德所羅門碼和convolutional codes時的最大功率消耗為141mW。和其他針對前端錯誤更正機制設計的數位訊號處理器比較起來，在程式大小方面改善了50%，在資料處理量上增大了66%。

In this thesis, an application specific digital signal processor (AS-DSP) for channel coding is presented. The proposed AS-DSP features vector operations, which can improve both the performance of memory accesses and program code density. The special function units and datapaths for channel decoding accelerate the decoding speed and facilitate algorithm implementation. The processor had been fabricated in a 0.18μm CMOS 1P6M technology. The gate count after synthesis is 139.4k and the chip size is 7.73mm2 including 18k bits embedded memory. The power consumption is 141mW while decoding Reed-Solomon code and convolutional code. In contrast with general purpose processor designs, the results show this chip has at least 50% improvement in code density and 66% data rate enhancement.