用於射頻積體電路模擬的閘極電阻準確模型

Abstract

當矽晶氧半場效電晶體（MOSFET）的通道長度不斷縮短下，其高頻特性將獲得極大的改善。然而，它的模組也將變得更複雜。一般常用的電路模擬模型是利用直流與簡單的電容模組所組成，這種模型只能大略估計元件的高頻特性到截止頻率（ft）的幾分之一。正因如此，研究元件的高頻特性並把它植入在小訊號模型的參數裡，以便進行電路模擬是很重要的。換句話說，一個先進的射頻（RF）模組，要考慮到閘極電阻（Gate Resistance）與通道所造成的影響，才能在大範圍的操作偏壓內，準確預估元件的高頻行為。 在本研究論文中，所有的分析是建立在通道長度為0.18μm的N型矽晶氧半場效電晶體上。從所萃取到的資料來看，我們發現閘極電阻與操作偏壓以及溫度都有很大的關連，這會嚴重影響到元件的高頻特性表現（如Y11,Y21）。我們首次發展一個較具物理意義且簡單的閘極電阻模型，它可以植入Spice電路模擬器中。此模型是以並聯閘極本質電阻與受通道影響所產生的電阻而形成。依據此閘極電阻模型所得到的模擬結果，遠比傳統固定閘極電阻的模型來的準確。舉例來說，傳統閘極模型將高估Y11的值，但包含偏壓與頻率效應的新模型卻可得到準確的模擬結果。 除此之外，我們還計算在不同偏壓下，矽晶氧半場效電晶體的通道鬆弛時間（Relaxation Time），並且利用Spice模擬它對元件在高頻的影響。此鬆弛時間所造成的非類穩態效應（Non-Quasi-Static effect）可用一個簡單的RC電路來模擬。另外，我們首次探討高頻參數的溫度效應。閘極電阻與鬆弛時間將隨溫度上升而變大，並且降低電流增益。相反的，閘極電容不隨溫度而改變。換句話說，在高溫下，閘極電阻與鬆弛時間將會嚴重影響到元件的高頻表現。 總而言之，本論文所提出的閘極電阻模型，能精確預測元件高頻行為且有助於射頻積體電路設計的電路模擬用途。

As the gate-length of a MOSFET reduces, its high-frequency characteristics can be greatly improved. However, its model becomes more complicate. Current Spice models are based on dc measurement data and simple capacitance models which can only approximate the high-frequency device characteristics up to a fraction of the device unity current gain frequency (ft). Thus, it is important to investigate the high-frequency characteristics and then incorporate the small-signal equivalent circuit parameters in Spice. On the other hand, an advanced RF model by considering the distributed effects in both gate and the channel is needed to accurately describe the RF behavior of device over a wide bias range. In this thesis, an analytical expression of the y-parameter is established and calibrated against measurements from a 0.18mm NMOSFET. From the extracted data, we found that the gate resistance depends largely on the bias and temperature. It will greatly impact the device performance at high frequency (e.g., Y11, Y21). For the first time, a simple physical-based gate resistance model is developed in this thesis and can be implemented in Spice. The gate resistance is modeled by a parallel interconnection of the intrinsic gate resistance and a resistance coupled from the channel. The Spice simulation result of this model is more accurate than that of a constant Rg model. A constant Rg model will overestimate the value of Y11, however, the proposed nonlinear gate resistance model with both bias and frequency dependent features can achieve very good accuracy. Furthermore, we calculate the relaxation time of the MOSFET at various bias, and show the Spice simulation result. The non-quasi-static effect due to the relaxation time can be simulated easily with a simple RC series network. Besides, the temperature effect of RF parameters were studied first. The gate resistance and the relaxation time increase with temperature and then reduce the current gain. In contrast, the gate capacitance remains a constant at different temperatures. In other words, the gate resistance and the relaxation time affect the device performance seriously at high frequency and high temperature. In summary, the proposed gate resistance model is important for RF circuit simulation and can predict the RF behavior of device accurately.