完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 鄭鍵樺 | en_US |
dc.contributor.author | Chein-Hua Cheng | en_US |
dc.contributor.author | 吳錦川 | en_US |
dc.contributor.author | Jiin-Chuan Wu | en_US |
dc.date.accessioned | 2014-12-12T02:25:37Z | - |
dc.date.available | 2014-12-12T02:25:37Z | - |
dc.date.issued | 2004 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT009211644 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/67224 | - |
dc.description.abstract | 隨著積體電路製程技術的日新月異,處理器的運算速度愈來愈快,單位時間內處理的資料量也日益增多,通常,傳輸介面的電路所能達到的單位時間最大傳輸量往往是整體系統速度的關鍵限制,因此,本篇論文是描述一個應用於高速串列數位影像傳輸介面,使用低擺幅差動訊號傳輸之傳送器的設計,並致力於設計此傳送器之資料傳輸速度操作在 2Gbps 。 傳送器由一個四相位鎖相迴路、虛擬隨機位元串列產生器、二對一多工器和一擁有預先加強電路設計之輸出驅動器所組成,其中,四相位鎖相迴路的輸入頻率為125MHz,輸出為四個相位 平均分佈且頻率同為1GHz的時脈訊號,所包含的電路有相位/頻率偵測器、電荷幫浦、迴路濾波器、兩級差動壓控振盪器和一個除八的除頻器。此鎖相迴路所產生的平均分佈時脈提供給虛擬隨機位元串列產生器和二對一多工器,並將一組並列資料轉為串列輸出,再經由輸出驅動器並搭配預先加強電路,來增加傳送資料位元轉變期間所需的電流量,最後,將此串列資料傳送至傳輸線上,即完成整個傳送器的設計。 此傳送器採用 TSMC 0.35μm 2P4M CMOS製程技術實現,當鎖相迴路輸入時脈為66.67MHz時,傳送器能正常傳送出1066.67Mbps的串列資料。 | zh_TW |
dc.description.abstract | As the advancement of IC fabrication technology, the operation of processors has sped up. The amounts of data processed in each unit time become larger and larger as time goes by. For most of time, the key limitation of a whole system is the maximum data amounts of the transmission interface circuit transmitted in each unit time. Therefore, the thesis describes the design of a transmitter for a high-speed serial digital display interface by RSDS technique. We have devoted to design the data rate of the transmitter at 2Gbps. The transmitter is composed of a four-phase PLL, PRBS circuits, 2-1 multiplexers and an output data driver with a pre-emphasis circuit. Among these devices, the input frequency of the four-phase PLL is 125MHz; it outputs four uniformly distributed clocks with 1 GHz frequency. The PLL comprises a Phase/Frequency Detector, a Charge Pump, a Loop Filter, a two-stage differential VCO and a divided-by-eight divider. It offers the PRBS and the 2-1 multiplexer with four uniformly distributed clocks to convert parallel pseudo-data into serial stream. Then, the serial data is transmitted by an output data driver with the pre-emphasis circuit. The pre-emphasis circuit is designed to increase the current during the data transition. In the end, the transmitter drives the serial data onto the transmission bus. The transmitter is implemented in the TSMC 0.35μm 2P4M CMOS process. When the input reference frequency is 66.67MHz, the transmitter can transmit serial data at 1066.67Mbps successfully. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 低擺幅差動訊號傳輸 | zh_TW |
dc.subject | 傳送器 | zh_TW |
dc.subject | RSDS | en_US |
dc.subject | Transmitter | en_US |
dc.title | 2Gbps 低擺幅差動訊號傳輸之傳送器 | zh_TW |
dc.title | A 2Gbps Reduced Swing Differential Signaling (RSDS) Transmitter | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
顯示於類別: | 畢業論文 |