金屬閘極之金氧半元件平帶電壓穩定性研究

Abstract

本論文探討不同氮/鉭成分比的氮化鉭薄膜功函數可調性以及氮化鉭、鉭和鉑閘極之金氧半元件平帶電壓穩定性。此外，亦探討氮化鉭阻障銅擴散的能力。吾人在含有不同氮/氬比例的氣體環境下，以反應式濺鍍方法沉積出不同氮/鉭成分比的氮化鉭薄膜，並在純氬氣體環境下沉積鉭及鉑薄膜。吾人以金屬/二氧化矽/矽基板結構在氮氣環境下做不同溫度爐管退火處理，探討氮化鉭、鉭及鉑金屬閘極元件之平帶電壓穩定性。藉由對氮化鉭、鉭及鉑金氧半元件的基本特性了解，吾人提出一用以選擇金氧半元件閘極材料之準則。 在氮化鉭方面，氮/鉭比從0.3增加至0.65功函數由4.14增加到4.21電子伏特，調變量不大，僅適用於n型金氧半場效電晶體。在熱穩定方面，當氮/鉭比達0.65後，加熱到400℃以上，則行成Ta3N5化合物，電阻係數大幅增加，其他條件都可以承受800℃的製程，沒有電阻增加現象。在600℃退火處理後，銅即穿透氮化鉭層，擴散進入閘介電層及矽基板。但是製程的溫度上限尚受另一因素控制，金屬閘極元件受熱應力影響，使得平帶電壓飄移且變異高達100毫伏以上。因此，銅/氮化鉭閘極元件可耐最高溫約為500℃。 在鉭方面，金屬功函數約為4.57電子伏特。元件在400℃到800℃不同溫度退火處理後，平帶電壓變異保持在23毫伏下，然而超過600℃退火處理，鉭和二氧化矽反應生成氧化鉭化合物並且熱應力造成平帶電位惡化。因此，鉭金屬閘極元件的最高製程溫度仍約為500℃。 在鉑金屬方面，金屬功函數約為5.38電子伏特。鉑薄膜熱穩定性可以高達800℃。然而，熱應力造成閘極絕緣層寄生電荷使得平帶電壓飄移量及變異量分別高達0.57伏特和600毫伏。過高的功函數及熱應力使得鉑金屬並不適合作為金屬閘極。 依據ITRS藍圖，臨限電壓的三倍標準差在0.07微米製程世代必須小於25毫伏。微小的變異量限制了可用的金屬閘極材料選擇及整合方式，在高溫處理後，能保有無結晶結構或可忽略的晶相轉換以及晶粒成長的薄膜會是較好的金屬閘極材料，至於製程的最高溫度必須考慮熱應力所導致的平帶電壓穩定性及變異量。

This thesis investigated the work function adjustability of TaNx films and the flat-band voltage stability of TaN-, Ta-, and Pt-gate MOS devices. The Cu barrier of TaNx films is also examined. The TaNx films were deposited by reactive sputtering in different ambient argon-nitrogen mixtures, with different Ar/N2 ratios; Ta and Pt films were deposited in pure Ar mass ambient. Samples with metal/SiO2/Si structures annealed at different temperatures in furnace in N2 ambient were used to analyze the thermal stability of the flat-band voltage. Several important features were observed and the guidelines for choosing metal gate materials were derived. The work function increases from 4.14eV to 4.21eV as the N/Ta ratio increases from 0.3 to 0.65. The range is small. Restated, TaNx is fit for use as a gate material in nMOSFET. Ta3N5 phase forms following a thermal process at 400℃ if the N/Ta ratio is as high as 0.65. This phase obviously increases in terms of resistivity When the N/Ta ratio is lower than 0.5, the resistivity remains stable up to 800℃. After annealing at temperatures higher than or equal to 600℃, copper diffuses into the substrate. The flatband voltage is significantly degraded by thermal stress and Cu ions. The highest sustainable process temperature after Cu/TaNx deposition is about 500℃. The work function of the Ta film is about 4.57eV. The flat-band voltage deviations of samples annealed at 400 to 800℃ are all below 23mV. In thermal annealing at above 600℃, Ta interacts with SiO2 to form a Ta-O compound and the flat-band voltage is seriously degraded by the thermal stress. The process temperature of the Ta gate should be approximately 500℃. The work function of the Pt film is about 5.38eV. Pt film is thermally stable up to 800℃. However, the high thermal stress generates many interface states and fixed charges, leading to a flat-band voltage variation of more than 0.57V. A flat-band voltage deviation as high as 600mV was also observed after thermal annealing at 600℃. Pt is not suitable for use as a gate electrode of MOS devices because of its high work function and high thermal stress. According to the ITRS roadmap, the 3σ variation of threshold voltage must be lower than 25mV following a 0.07μm technology node. The small flat-band voltage deviation creates an additional criterion for choosing the metal gate material and the integration scheme. Films with amorphous structures, negligible grain growth, and a negligible phase transformation at high temperature are preferred to eliminate deviation for metal gate materials. The highest process temperature is also determined by the stress induced flat-band voltage variation and deviation.