以FPGA設計與實證之DS-3 DQPSK數據機

Abstract

本論文中我們以FPGA設計與實證了一個DS-3 DQPSK數據機。此數據機包含傳送機和接收機。傳送機包含串列到並列的轉換器、單極性到雙極性的轉換器、差分編碼器、有限脈衝響應低通濾波器和數位化實行的I/Q 調變器。 而接收機則包含延遲電路、定點數運算乘法器、有限脈衝響應低通濾波器、決策電路和並列到串列的轉換器。所有此些元件均被我們所設計、模擬與驗證，而最後被實行在單一FPGA晶片上。

In this thesis, we design and implement an FPGA-based DS-3 DQPSK Modem. The transmitter is composed of a serial to parallel converter, an uni-polar to bi-polar converter, a differential encoder, an FIR LP filter and a digitally implemented I/Q modulator. The receiver is composed of a delay circuit, a fixed-point multiplier, an FIR LP filter, a decision circuit and a parallel to serial converter. All of these parts are designed, simulated and verified, and finally implemented on a single FPGA chip.