1.2Gbps更小擺幅差動訊號傳輸模式收發器

Abstract

由於積體電路製程上技術的進展，在晶片間的資料傳輸所要求的速度與傳輸資料量也因應的提升，但如何在達到高速傳輸的目的下卻不造成空間與功率的浪費，而在現今以高速序列傳輸方式為主流中，具有高速、低功率、低雜訊干擾特性的(RSDS)更小擺幅差動訊號傳輸方式的技術是頗受歡迎的。 本篇論文在研究RSDS傳輸模式下以1.2Gbps的傳輸速度運作的收發器架構，當中分為傳輸與接收兩個部份，並以tsmc 0.352P4M CMOS的製程技術在電壓電源為3.3V的情況下進行模擬。 傳輸器利用一個鎖相迴路來提供時脈和多工器將資料由並列轉為序列輸出。鎖相迴路的輸入頻率為75MHz，輸出頻率鎖在150MHz並提供八個相位的時脈給多工器使用，並在時脈與資料間先進行預先位準調整，再經由八對一多工器輸出可得1.2Gbs的資料頻率輸出，該接收器的消耗功率為134mW。 接收器使用一具磁滯現象比較器將接收訊號放大為數位訊號。再利用一操作在輸入資料一半頻率、且具有頻率、相位雙向追蹤的時脈資料回復電路來將資料與時脈對準，最後由一對八解多工器將資料轉回並列。該接收器的功率消耗為164mW。

Due to the improvement of IC fabrication technology, the speed and amount of inter-chip data transmission has also been required more. The problem is how to make high speed transmission without wasting space and power. Among the main stream, high speed serial ports, RSDS technology with high speed, low power and low EMI character is popular now. This thesis describes the design of a high-speed RSDS transmission interface with 1.2Gbps rate. The transceiver includes transmitter and receiver and is simulated in a TSMC 0.35μm 2P4M process and at 3.3V supply voltage. The transmitter makes use of a PLL to provide the 8-phase, 150MHz clock for the multiplexer and translate the parallel data to be serial and the input frequency of PLL is 75MHz.The data and clock is pre-skewed to adjust the accuracy .Then with the 8-phase clock and 8 to 1 multiplexer, the output data can be transmitted at 1.2Gbps data rate. And the total power of the transmitter is 134mW. The receiver uses the comparator with hysteresis to amplify the incoming data to full swing, and uses (CDR) clock and data recovery with phase and frequency detectors to lock the clock with better jitter performance. Finally, the 1 to 8 de-multiplexer converts the CDR output to 8 parallel data channels. The total power of receiver is 164mW.