OPTIMIZATION AND MODELING FOR MOS VARACTORS IN 65 nm LOW-POWER MIXED-SIGNAL/RADIO-FREQUENCY TECHNOLOGY

Abstract

CMOS technology scaling opens tip the possibility of designing variable capacitors based oil a metal oxide semiconductor (MOS) structure with improved tuning range and quality factor. In this work, the high Q-factor 24 and 21, wide timing ratio 45% and 36% can be achieved by 65 nm low power technology n+/n-well and p+/p-well MOS varactor up to 10 GHZ, respectively. Meanwhile, the equivalent circuit model, to model intrinsic and extrinsic parameters of MOS varactor, also have demonstrated that parasitic resistance is a main issue to dominate Q-factors, and the measured flicker noise result of MOS varactor is directly dependant on gate leakage current. (C) 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2119-2121. 2009; Published online in Wiley InterScience (www.intescience.wiley.com). DOI 10.1002/mop.24567