考慮緩衝器最佳躍遷時間之低功率時鐘樹生成

Abstract

隨著製造技術的進步，有百萬個或千萬個閘在電路中，這使得時鐘網路設計上會有很大的挑戰，由於電路頻率愈來愈高，所花費的功率也越來越多，且大部分都在時鐘樹本身，如沒有小心的規劃時鐘網路，電路將承受高功率的損耗。在本篇論文中，我們發展出一個方法能夠在時鐘樹合成時，達到低功率的效果。此方法基本上根據分析任意提供的緩衝器資料庫，進一步發現最佳的躍遷時間來有效的插入緩衝器，達到低功率的成果。由實驗結果可以得知，我們的方法能有效的降低功率。跟之前的利用調整閘大小的方法，我們能夠減少平均百分之十以上的功率損失而且較小的非對稱時鐘差。

Clocking has been playing a very important role in current VLSI designs. As technology advances, there exist millions or billions of gates on a chip, which makes the clock network design much more challenging since synchronization in chip is one of the primary concerns. However, chips running at higher frequency consume much more power, mostly on clock distribution. Without carefully planning clock network, the chips will suffer from high power dissipation. In this thesis, we develop a methodology which can be applied in buffered clock tree synthesis to achieve low power demands. It is based on the analysis of any given buffer library in finding best transition time for low power and customized buffer insertion. The experimental results are encouraging. We have obtained average up to 10% power saving and smaller clock skew compared with a previous work based on gate sizing.