以閘極感應與通道感應方法與脈衝電流電壓技術分析SONOS類型元件中捕捉電荷之特性

Abstract

本篇論文主要致力於，利用許多新穎的技術廣泛地研究SONOS類型元件之電荷捕捉特性，以求對於SONOS類型元件的物理特性有更深入地了解。由於SONOS類型元件擁有絕佳的微縮能力及少數電子儲存性等優勢，使它被認為會是在未來微縮時代中，最可能取代快閃(Flash)記憶體的其中一者。縱使如此，人們對於SONOS類型元件中，氮化層捕捉電荷行為的了解，仍然是非常有限的。在本篇論文裡，我們首先提出一個新穎的閘極感應與通道感應(gate-sensing and channel-sensing, GSCS)方法。除了傳統通道感應型(CS)電容，我們又多加了另一個閘極感應型(GS)電容。利用這兩種不同感應型態的電容，我們可以得到兩個方程式。而這兩個方程式正好可以讓我們解兩個變數。一個是總電荷密度(Q)，另一個則是電荷的平均垂直位置(x)。這個方法有幾個相當大的優勢，它不需要複雜的儀器設備，也不需要在比較不同樣品時做一些人工的參數調整，以求符合實驗的數據。因此，我們可以說是提出了一個相當簡單且有力的方法，來研究捕捉電荷的特性。透過這方法，我們可以偵測在”真實時間”內捕捉電荷的位置、寫入抹除時氮化層內部電荷傳輸的行為以及各種可靠度的分析。我們也驗証了被捕捉的電子主要是分佈在整個氮化層裡而非在氧化層與氮化層之間的界面。此外，在本篇論文裡，我們也詳盡地描述各種堆疊氮化層的捕獲效率、氮化層內部的電荷傳輸以及各種可靠度問題。基於GSCS方法，我們也提出了一個系統化的方法來區別SONOS類型元件的抹除機制 (是來自於外部電洞的注入或是被捕捉的電子從氮化層逃脫出來)。 除了GSCS方法之外，我們也為記憶體未來應用性及其快速缺陷特性化發展出一種新的脈搏電壓電流(Pulse-IV)技術。Pulse-IV技術最近已經被廣泛地應用在CMOS邏輯元件，研究其高介電常數閘極介電層中陷阱的特性。在本篇論文裡，我們進一步改進舊有的Pulse-IV技術，使它能夠應用在記憶體的相關研究上。我們研究了SONOS電容的瞬間暫態穿隧電流，並且發現穿隧電流的暫態變化是與元件的電荷捕捉行為及其堆疊結構有關。然而，這個Pulse-IV技術最值得注意的應用，是在於研究SONOS電晶體的超快速穿隧注入。我們的Pulse-IV技術可以準確且即刻地描述電晶體在寫入抹除後的行為，而沒有任何讀取干擾問題。我們可以準確地提供在微秒等級內元件的特性。而這個新技術也替研究類似非揮發性記憶體的應用開闢了一條嶄新的道路。

This dissertation is devoted to study the charge trapping characteristics of SONOS-type devices extensively by several new techniques and provide in-depth physical understanding. Although SONOS-type devices are forecasted to be the promising solutions to continue the Flash memory scaling due to their excellent scalability and few-electron storage capability, the fundamental understanding of the nitride-trapping behaviors is still very limited. In this dissertation, we first proposed a novel gate-sensing and channel-sensing (GSCS) method, where an additional GS capacitor is used to compare with the conventional CS one. Sensing in both modes provides two equations that are suitable to solve for two variables — the total trapped charge density (Q) and the average charge vertical location (x). This method does not need complex equipment or artificial fitting in comparing different samples, thus provides a very simple and powerful method to characterize trapped charge. Through this method we could monitor in “real-time” the trapped charge location and intra-nitride behaviors during programming/erasing as well as retention reliability test. We also clarified that the electrons are mainly distributed inside the bulk nitride instead of the interfaces between oxide and nitride. Furthermore, the capture efficiency of various stacked nitride-trapping layers, intra-nitride transport, and reliability issues were investigated in detail. Based on GSCS method, we also provided a systematic method to distinguish the erase mechanisms by hole injection from that by electron de-trapping for SONOS-type devices. In addition to GSCS method, we also developed a new Pulse-IV technique for memory applications and fast trap characterizations. Pulse-IV techniques have been developed recently to characterize traps in high-k gate dielectrics of CMOS logic devices. In our work we have improved this technique to apply in memory characterizations. The transient tunneling currents of various SONOS-type capacitors have been studied in detail, and we found that the tunneling current relaxation is well correlated to charge trapping and memory structures. Moreover, the power of this pulse-IV is fully demonstrated when studying SONOS-type transistors with very fast tunneling injection. Our pulse-IV technique can accurately characterize the transistors immediately after programming/erasing without read disturbance and provide accurate device characterizations within microsecond. This new characterization method also opens a new path to study quasi-non-volatile memory applications.