新嵌入式內層導線與低介電常數材料化學機械研磨之研究

Abstract

在積體電路工業技術持續的進步之下，元件的設計日趨複雜，深次微米結構的需求也日益的增加。因此晶圓表面的平坦度必須提高，以配合微影技術的要求，綜合及大型積體電路金屬化新近發展的平坦化技術中，化學機械研磨 ( Chemical Mechanical Polish ) 是目前可達到全域性平坦化的技術。而在元件尺寸的縮小及積極度增加的情況之下，多層導線所造成的RC延遲也相對的增加。為了解決此問題，銅導線的運用與低介電常數絕緣材料的引進也就成為日後發展的重要因數。在低介電常數材料方面，由於高分子材料具有低薄膜應力與低介電，而成為經屬導線間最佳的絕緣材料。但由於其化學不活潑性與柔軟性，也造成在化學機械研磨方面的重大挑戰。本論文也就針對此問題對高分子低介電材料在經過化學機械研磨後，所產生的物理和化學變化來做探討。 並且也提出一種新的製程，配合無電鍍法來建構我們的內層導線。而此法也可配合日後所發展出的新低介電材料之運用，並藉此新的製程技術來改善銅導線在經由化學機械研磨後所造成的一些問題。

When the device dimension is shrink, the RC delay becomes the dominant performance limiting factor. In order to Improve the RC delay time, Cu is used to replace the conventional Al. Due to it has the lower resistivity ( 1.67 □Ω-cm ) and high electromigration resistance. Moreover integration with low-k dielectric is a way to reduce the interconnect contribution to the parasitics. Using low-k materials as intra/interlevel-dielectric ( ILD ) have led to a significant reduction in intralevel and interlevel capacitance. In comparison to the conventional Al wiring and oxide ILD interconnect of the some dimension, about 30% conductivity, 20% intralevel and 30% interlevel capacitance improvement has been observed in the Cu/low-k interconnect. SiLK is a polymer low-k material film, the characterizations of physical and chemical are soft and inert. So in order to understand the alteration of characterizations of physical and chemical during over-polishing, we designed some experiments to research SiLK CMP. In general, the damascene process is popularly used in ULSI process. but it often results some problems. For example, as we use CMP to polish the metals over the trenches will induce copper dishing and oxide erosion. Those will decrease circuit performance. So we bring up a novel damascene process.