以無電電鍍技術沈積鎳/銅凸塊以供覆晶接合應用之研究

Abstract

本實驗以無電電鍍（Electroless Plating）技術，配合微影成像與蝕刻技術，進行埠端重佈及覆晶構裝（Flip Chip Package）之鎳/銅雙層金屬凸塊（Metal Bump）製作，以應用於高頻III-V族元件之構裝。無電鍍銅的原料成本比無電鍍金更為低廉，且銅又具有優良的導電性（電阻率 = 1.7 μΩ-cm）、良好抗電子遷移及良好的抗應力導致的空洞形成性質，故本實驗以無電鍍鎳及無電鍍銅為金屬線路及金屬凸塊之材料，並比較拋光與未拋光之氮化鋁（Aluminum Nitride）基板上所沈積之無電鍍鎳和無電鍍銅之表面型態及電阻率差異，實驗結果顯示氮化鋁在經研磨拋光之氮化鋁表面，沈積之無電鍍金屬具有較平整且緻密之金屬薄膜，電阻率也較沈積在未研磨拋光表面者低。此外，在拋光面之氮化鋁基板上以蝕刻技術形成鎳金屬線路，再以微影成像技術定義出凸塊位置，進行無電鍍鎳15分鐘後去光阻再無電鍍銅30鐘，可完成厚度約2 μm之無電鍍鎳/銅之雙層線路及高度約5 μm之金屬凸塊之結構。

This thesis employed the electroless plating technology, accompanying with the photolithography and etching process, to prepare Ni/Cu double-layered metal bumps for flip chip packaging of high-frequency devices. The electroless plating of Cu is relatively inexpensive. Further, Cu has superior conduction property（Resistivity = 1.7 μΩ-cm）, resistance to electromigration and stress-induced void formation. We hence adopted the electroless plating Ni and Cu to fabricate the metal lines and bumps. We compared the difference on surface morphology and resistivity for the deposition film on polished and unpolished AlN substrates. The results showed that the electroless deposited film on a polished AlN surface exhibits a more uniform surface morphology and lower resistivity than the unpolished one. In addition, by forming Ni metal line on AlN substrate within photolithography process, We were able to accomplish the structure of 2μm thick Ni/Cu double layer metal lines and 5μm thick metal bumps by using the electroless plating technique.