非晶矽覆蓋層形成超淺接面在奈米MOS元件之應用

Abstract

本論文中，我們提出一種應用在奈米MOS元件形成超淺接面的方法。隨著元件的微小化，短通道效應日趨嚴重。 超淺接面的形成則可以減輕穿遂效應及短通道效應。本文提出一種可以利用既有的離子佈植和快速退火技術，無須低能量離子佈植機台以形成超淺接面的方式。Diffusion from implanted amorphous silicon (DIA) 是以離子植入非晶矽覆蓋層，接著以此非晶矽層作為退火時的固態擴散源的方式形成淺接面。在非晶矽層之下，我們加疊一層氧化層以作為蝕刻時的阻擋層。由於這種非晶矽-氧化層的雙層結構可以容易去除非晶矽層，它可以提供良好的製程控制能力及提高元件的可靠度。利用非晶矽覆蓋層作為形成接面的擴散源，更能減少因離子佈植所造成的缺陷。我們因此可以形成幾乎無缺陷的超淺接面。我們同時也在DIA接面中加入氟離子，以探討氟對於接面特性的影響。另外，我們也將DIA接面與鈦/鎳多層疊金屬結構的矽化鎳製程合併。DIA結構可以減少在矽化鎳接面邊際上的缺陷數量。因此，這種方式形成的接面有良好的電性及接面特性，得以符合未來MOS技術之發展。

In this thesis, we have proposed a new ultra-shallow junction formation method for nano-MOS technology applications. As device dimension scales down, the short channel effects become more serious. Formation of ultra-shallow junctions is essential to minimizing punch-through and short channel effects. This thesis presents a method to fabricate ultra-shallow junctions using present ion implantation and rapid thermal annealing techniques without requirement of low energy implant equipments. Diffusion from implanted amorphous silicon (DIA) is performed by junction implant through an amorphous capping layer; the amorphous layer thus acts as a surface solid diffusion source during annealing. A thin oxide is deposited to serve as etching stop layer beneath the amorphous layer. This bilayer amorphous-oxide structure enables easy removal of the amorphous layer and provides good process control and device reliability. By using amorphous silicon layer as the diffusion source for junction formation, implant defects are reduced. Defect-free ultra-shallow junctions can be formed. DIA junctions are also co-implanted with F to observe the effect of F on junction characteristics. Finally, DIA junctions combined with Ti capped Ni silicide processes have been fabricated. The DIA structure has been found to reduce periphery junction defects. These junctions exhibit good electrical and junction characteristics suitable for the future MOS technology.