鐵電記憶元件製程及特性之研究

Abstract

現今商業化的一電晶體一電容鐵電記憶體在讀取上是具有破壞性的。本實驗直接探討非破壞性結構的製程條件與特性。一系列的參數模擬被應用來導引實驗方向，並以SBT和BIT兩種鐵電材料探討在不同回火溫度處理下的電學特性及比較，”金屬-鐵電膜-金屬-絕緣層-矽基板”結構被應用來調變鐵電電容與絕緣層電容的比值，以加強在低操作電壓下記憶窗的寬度，並以模擬結果相互映證;同時嘗試以高介電鈣鈦礦結構的STO材料取代二氧化矽絕緣層，進一步增強低電壓操作的可能行，最後探討此結構以及STO材料整體的可靠度特性。

At the present time, the commercial 1T1C(1 transistor 1 capacitor) ferroelectric memory is a destructive readout. Our experiments here directly investigate the process conditions and characteristics of non-destructive structure. A sequence of parameter simulations has been utilized to guide the experiments. The electrical properties and comparison of ferroelectric materials, including SBT and BIT, are investigated under different annealing conditions. To enhance the memory window under low voltage operation, “metal/ferroelectric/metal/ insulator/semiconductor” structure is utilized to adjust the ratio of ferroelectric and insulating capacitance and verified with simulation results. Meanwhile, for the reason of further probability to achieve low voltage operation, STO material with high-k perovskite structure is used to replace the traditional SiO2 insulator. Finally, the reliability properties of the structure and STO material are investigated.