堆疊式閘極介電層結構之低溫多晶矽薄膜電晶體特性之研究

Abstract

在本論文中，我們提出堆疊式閘極介電層結構之低溫多晶矽薄膜電晶體，以電漿輔助化學氣相沈積系統兩段式製程步驟連續成長此堆疊氧化層。此堆疊式閘極介電層是由N2O電漿氧化層與TEOS氧化層所堆疊組成，具有極佳的電特性，比傳統低溫多晶矽氧化層有更高的崩潰電場 ( > 8.5 MV/cm)。我們更進一步將此堆疊式氧化層應用於低溫多晶矽薄膜電晶體上，大幅的提升TFT元件電特性及可靠度，比起傳統的薄膜電晶體有更低的臨界電壓(下降4伏)、更低的次臨界搖擺(改善1 V/dec)、更高的開關電流比 (> 3.5x106)，在場效移動率方面更大幅改善五倍之多。TFT元件電特性之所以有如此明顯的改善，乃是N2O電漿成長的高品質超薄氧化層與多晶矽形成平坦並有極強Si≡N鍵結的介面，並且成長過程中的N2O電漿鈍化機制（passivation）引致大量的氮原子與氧原子修補多晶矽的缺陷所造成的改善。 最後，為了更進一步改善元件特性，我們提出不同方式的鈍化技術處理來降低缺陷密度和改善TEOS氧化層的品質，其中我們所使用的技術為PECVD氨氣（NH3）電漿處理、笑氣（N2O）電漿處理以及在400℃使用爐管通入氧氣或笑氣試圖緻密化與改善氧化層品質。研究發現經過氨氣電漿處理之元件有最佳的電性，乃是由於氫原子的鈍化效果填補多晶矽中的缺陷並降低缺陷態位（defect states），在介面上氮原子的堆積形成強化的Si≡N鍵結等原因所造成的電性改善。

The low temperature polysilicon thin-film transistors (TFTs) have been used in a wide variety of applications in active matrix liquid crystal displays (AMLCDs). Thus, conventional high-temperature thermal oxidation was not suitable for them due to glass substrates. Therefore, the low temperature process of high quality gate dielectric film is necessary for TFTs device fabrication. In this thesis, low-temperature poly-Si TFTs with a novel stack dielectric structure in-situ grown by plasma-enhanced chemical vapor deposition (PECVD) system were presented. The novel stack dielectric is composed of N2O-plasma grown oxide and TEOS oxide has superior electrical properties. The stack oxide grown on poly-Si films shows higher breakdown fields (8.4 MV/cm) than traditional TEOS oxide. The fabricated poly-Si TFTs with a novel stack oxide show high performance characteristics, including smaller threshold voltage, smaller subthreshold swing, higher on/off current ratio (> 3.5x106), especially in the field effective mobility increased more than five times, and also remarkable reliability. These improvements were attributed to the high quality N2O-plasma grown oxide forming smoother surface and strong Si≡N bonds in the oxide/polysilicon interface. In the other hands, N2O-plasma passivation effect induces large amount of nitrogen and oxygen atoms passivated the traps in the polysilicon grain boundaries. Finally, we further proposed different kinds of passivation methods for achieving higher quality gate oxide and reducing polysilicon trap density for promoting the electrical properties of poly-Si TFTs. These methods include NH3-plasma passivation, N2O-plasma passivation, and annealed in O2 or N2O furnace ambient. It was found that proposed poly-Si TFTs after NH3-plasma directly passivated on stack oxide exhibited significantly superior devices characteristics to others due to the hydrogen passivation of defects and traps, and the nitrogen pile-up at the SiO2/poly-Si interface and the strong Si≡N bonds formation to passivate the dangling bonds at the grain boundaries in the polysilicon.